Lines Matching full:present

12  * A MMU present SPTE is backed by actual memory and may or may not be present
13  * in hardware.  E.g. MMIO SPTEs are not considered present.  Use bit 11, as it
15  * better code than for a high bit, e.g. 56+.  MMU present checks are pervasive
64  * as not-present for access tracking purposes. We do not save the W bit as the
131  * MMU-present bit.  The generation obviously co-exists with the magic MMIO
132  * mask/value, and MMIO SPTEs are considered !MMU-present.
134  * The SPTE MMIO mask is allowed to use hardware "present" bits (i.e. all EPT
155  * Non-present SPTE value needs to set bit 63 for TDX, in order to suppress
156  * #VE and get EPT violations on non-present PTEs.  We can use the
159  * For SVM NPT, for non-present spte (bit 0 = 0), other bits are ignored.
202  * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
215  * non-present intermediate value. Other threads which encounter this value
218  * Use a semi-arbitrary value that doesn't set RWX bits, i.e. is not-present on
226 /* Frozen SPTEs must not be misconstrued as shadow present PTEs. */
241  * In some cases, we need to preserve the GFN of a non-present or reserved
382  * A shadow-present leaf SPTE may be non-writable for 4 possible reasons:
443  * The Host-writable bit is not modified on present SPTEs, it is only set or
444  * cleared when an SPTE is first faulted in from non-present and then remains
452 /* Note: spte must be a shadow-present leaf SPTE. */
472  * SPTE is a shadow-present, leaf SPTE (either before or after).
503  * Note, this logic only applies to shadow-present leaf SPTEs.  The caller is
504  * responsible for checking that the old SPTE is shadow-present, and is also
506  * modifying a shadow-present non-leaf SPTE.