Lines Matching +full:queue +full:- +full:rx

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
40 /* Registers for MSI-X */
63  * Host-Device interface is active
64  * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
65  * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
74 /* Minimum and Maximum number of MSI-X Vector
86 /* The number of descriptors in TX/RX queues */
89 /* Number of Queue for TX and RX
98 /* The size of DMA buffer for TX and RX in bytes */
109 /* Number of pending RX requests for downlink */
121  * All members are write-only for host and read-only for device.
134  * @addr_tfdq: Address of TFD Queue(tx)
135  * @addr_urbdq0: Address of URBD Queue(tx)
136  * @num_tfdq: Number of TFD in TFD Queue(tx)
137  * @num_urbdq0: Number of URBD in URBD Queue(tx)
138  * @tfdq_db_vec: Queue number of TFD
139  * @urbdq0_db_vec: Queue number of URBD
140  * @addr_frbdq: Address of FRBD Queue(rx)
141  * @addr_urbdq1: Address of URBD Queue(rx)
142  * @num_frbdq: Number of FRBD in FRBD Queue(rx)
143  * @frbdq_db_vec: Queue number of FRBD
144  * @num_urbdq1: Number of URBD in URBD Queue(rx)
145  * @urbdq_db_vec: Queue number of URBDQ1
146  * @tr_msi_vec: Transfer Ring MSI-X Vector
147  * @cr_msi_vec: Completion Ring MSI-X Vector
220  * @num_txq: Queue index of TFD Queue
232 /* FRB Descriptor for RX
233  * @tag: RX buffer tag (index of RX buffer queue)
243 /* URB Descriptor for RX
254 /* RFH header in RX packet
256  * @rxq: RX Queue number
288 /* Structure for TX Queue
308 /* Structure for RX Queue
332  * @irq_lock: spinlock for MSI-X
333  * @hci_rx_lock: spinlock for HCI RX flow
335  * @msix_entries: array of MSI-X entries
336  * @msix_enabled: true if MSI-X is enabled;
349  * @workqueue: workqueue for RX work
350  * @rx_skb_q: SKB queue for RX packet
351  * @rx_work: RX work struct to process the RX packet in @rx_skb_q
358  * @txq: TX Queue struct
359  * @rxq: RX Queue struct
367 	/* lock used in MSI-X interrupt */
369 	/* lock to serialize rx events */
413 	return ioread32(data->base_addr + offset);  in btintel_pcie_rd_reg32()
419 	iowrite8(val, data->base_addr + offset);  in btintel_pcie_wr_reg8()
425 	iowrite32(val, data->base_addr + offset);  in btintel_pcie_wr_reg32()
433 	r = ioread32(data->base_addr + offset);  in btintel_pcie_set_reg_bits()
435 	iowrite32(r, data->base_addr + offset);  in btintel_pcie_set_reg_bits()
443 	r = ioread32(data->base_addr + offset);  in btintel_pcie_clr_reg_bits()
445 	iowrite32(r, data->base_addr + offset);  in btintel_pcie_clr_reg_bits()