Lines Matching +full:clock +full:- +full:accuracy
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/at91.h>
55 unsigned long accuracy; member
73 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_prepare()
76 if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) in clk_slow_osc_prepare()
79 writel(tmp | osc->bits->cr_osc32en, sckcr); in clk_slow_osc_prepare()
82 udelay(osc->startup_usec); in clk_slow_osc_prepare()
84 usleep_range(osc->startup_usec, osc->startup_usec + 1); in clk_slow_osc_prepare()
92 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_unprepare()
95 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_unprepare()
98 writel(tmp & ~osc->bits->cr_osc32en, sckcr); in clk_slow_osc_unprepare()
104 void __iomem *sckcr = osc->sckcr; in clk_slow_osc_is_prepared()
107 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_is_prepared()
110 return !!(tmp & osc->bits->cr_osc32en); in clk_slow_osc_is_prepared()
133 return ERR_PTR(-EINVAL); in at91_clk_register_slow_osc()
137 return ERR_PTR(-ENOMEM); in at91_clk_register_slow_osc()
145 osc->hw.init = &init; in at91_clk_register_slow_osc()
146 osc->sckcr = sckcr; in at91_clk_register_slow_osc()
147 osc->startup_usec = startup; in at91_clk_register_slow_osc()
148 osc->bits = bits; in at91_clk_register_slow_osc()
151 writel((readl(sckcr) & ~osc->bits->cr_osc32en) | in at91_clk_register_slow_osc()
152 osc->bits->cr_osc32byp, sckcr); in at91_clk_register_slow_osc()
154 hw = &osc->hw; in at91_clk_register_slow_osc()
155 ret = clk_hw_register(NULL, &osc->hw); in at91_clk_register_slow_osc()
177 return osc->frequency; in clk_slow_rc_osc_recalc_rate()
185 return osc->accuracy; in clk_slow_rc_osc_recalc_accuracy()
191 void __iomem *sckcr = osc->sckcr; in clk_slow_rc_osc_prepare()
193 writel(readl(sckcr) | osc->bits->cr_rcen, sckcr); in clk_slow_rc_osc_prepare()
196 udelay(osc->startup_usec); in clk_slow_rc_osc_prepare()
198 usleep_range(osc->startup_usec, osc->startup_usec + 1); in clk_slow_rc_osc_prepare()
206 void __iomem *sckcr = osc->sckcr; in clk_slow_rc_osc_unprepare()
208 writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr); in clk_slow_rc_osc_unprepare()
215 return !!(readl(osc->sckcr) & osc->bits->cr_rcen); in clk_slow_rc_osc_is_prepared()
230 unsigned long accuracy, in at91_clk_register_slow_rc_osc() argument
240 return ERR_PTR(-EINVAL); in at91_clk_register_slow_rc_osc()
244 return ERR_PTR(-ENOMEM); in at91_clk_register_slow_rc_osc()
252 osc->hw.init = &init; in at91_clk_register_slow_rc_osc()
253 osc->sckcr = sckcr; in at91_clk_register_slow_rc_osc()
254 osc->bits = bits; in at91_clk_register_slow_rc_osc()
255 osc->frequency = frequency; in at91_clk_register_slow_rc_osc()
256 osc->accuracy = accuracy; in at91_clk_register_slow_rc_osc()
257 osc->startup_usec = startup; in at91_clk_register_slow_rc_osc()
259 hw = &osc->hw; in at91_clk_register_slow_rc_osc()
260 ret = clk_hw_register(NULL, &osc->hw); in at91_clk_register_slow_rc_osc()
280 void __iomem *sckcr = slowck->sckcr; in clk_sam9x5_slow_set_parent()
284 return -EINVAL; in clk_sam9x5_slow_set_parent()
288 if ((!index && !(tmp & slowck->bits->cr_oscsel)) || in clk_sam9x5_slow_set_parent()
289 (index && (tmp & slowck->bits->cr_oscsel))) in clk_sam9x5_slow_set_parent()
293 tmp |= slowck->bits->cr_oscsel; in clk_sam9x5_slow_set_parent()
295 tmp &= ~slowck->bits->cr_oscsel; in clk_sam9x5_slow_set_parent()
311 return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel); in clk_sam9x5_slow_get_parent()
333 return ERR_PTR(-EINVAL); in at91_clk_register_sam9x5_slow()
337 return ERR_PTR(-ENOMEM); in at91_clk_register_sam9x5_slow()
345 slowck->hw.init = &init; in at91_clk_register_sam9x5_slow()
346 slowck->sckcr = sckcr; in at91_clk_register_sam9x5_slow()
347 slowck->bits = bits; in at91_clk_register_sam9x5_slow()
348 slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel); in at91_clk_register_sam9x5_slow()
350 hw = &slowck->hw; in at91_clk_register_sam9x5_slow()
351 ret = clk_hw_register(NULL, &slowck->hw); in at91_clk_register_sam9x5_slow()
395 child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc"); in at91sam9x5_sckc_register()
400 bypass = of_property_read_bool(child, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
402 child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow"); in at91sam9x5_sckc_register()
404 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
455 CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
462 CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc",
498 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in of_sam9x60_sckc_setup()
510 clk_data->num = 2; in of_sam9x60_sckc_setup()
515 clk_data->hws[SCKC_MD_SLCK] = hw; in of_sam9x60_sckc_setup()
523 clk_data->hws[SCKC_TD_SLCK] = hw; in of_sam9x60_sckc_setup()
532 at91_clk_unregister_sam9x5_slow(clk_data->hws[SCKC_TD_SLCK]); in of_sam9x60_sckc_setup()
534 clk_hw_unregister(clk_data->hws[SCKC_MD_SLCK]); in of_sam9x60_sckc_setup()
542 CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc",
549 if (osc->prepared) in clk_sama5d4_slow_osc_prepare()
556 if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) { in clk_sama5d4_slow_osc_prepare()
557 osc->prepared = true; in clk_sama5d4_slow_osc_prepare()
562 udelay(osc->startup_usec); in clk_sama5d4_slow_osc_prepare()
564 usleep_range(osc->startup_usec, osc->startup_usec + 1); in clk_sama5d4_slow_osc_prepare()
565 osc->prepared = true; in clk_sama5d4_slow_osc_prepare()
574 return osc->prepared; in clk_sama5d4_slow_osc_is_prepared()
624 osc->hw.init = &init; in of_sama5d4_sckc_setup()
625 osc->sckcr = regbase; in of_sama5d4_sckc_setup()
626 osc->startup_usec = 1200000; in of_sama5d4_sckc_setup()
627 osc->bits = &at91sama5d4_bits; in of_sama5d4_sckc_setup()
629 ret = clk_hw_register(NULL, &osc->hw); in of_sama5d4_sckc_setup()
634 parent_hws[1] = &osc->hw; in of_sama5d4_sckc_setup()
650 clk_hw_unregister(&osc->hw); in of_sama5d4_sckc_setup()
656 CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",