Lines Matching +full:0 +full:x53f80000
18 #define MX31_CCM_BASE_ADDR 0x53f80000
19 #define MX31_GPT1_BASE_ADDR 0x53f90000
22 #define MXC_CCM_CCMR 0x00
23 #define MXC_CCM_PDR0 0x04
24 #define MXC_CCM_PDR1 0x08
25 #define MXC_CCM_MPCTL 0x10
26 #define MXC_CCM_UPCTL 0x14
27 #define MXC_CCM_SRPCTL 0x18
28 #define MXC_CCM_CGR0 0x20
29 #define MXC_CCM_CGR1 0x24
30 #define MXC_CCM_CGR2 0x28
31 #define MXC_CCM_PMCR0 0x5c
55 clk[dummy] = imx_clk_fixed("dummy", 0); in _mx31_clocks_init()
75 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0); in _mx31_clocks_init()
91 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0); in _mx31_clocks_init()
107 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); in _mx31_clocks_init()
140 ccm = of_iomap(np, 0); in mx31_clocks_init_dt()