Lines Matching full:hw
64 .hw.init = &(struct clk_init_data){
81 .hw.init = &(struct clk_init_data){
85 &g12a_fixed_pll_dco.hw
129 .hw.init = &(struct clk_init_data){
148 .hw.init = &(struct clk_init_data){
152 &g12a_sys_pll_dco.hw
188 .hw.init = &(struct clk_init_data){
207 .hw.init = &(struct clk_init_data){
211 &g12b_sys1_pll_dco.hw
223 .hw.init = &(struct clk_init_data) {
226 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
240 .hw.init = &(struct clk_init_data) {
244 &g12b_sys1_pll.hw
257 .hw.init = &(struct clk_init_data){
261 &g12a_sys_pll_div16_en.hw
270 .hw.init = &(struct clk_init_data){
274 &g12b_sys1_pll_div16_en.hw
283 .hw.init = &(struct clk_init_data){
286 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
296 .hw.init = &(struct clk_init_data){
300 &g12a_fclk_div2_div.hw
320 .hw.init = &(struct clk_init_data){
323 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
333 .hw.init = &(struct clk_init_data){
337 &g12a_fclk_div3_div.hw
361 .hw.init = &(struct clk_init_data){
366 { .hw = &g12a_fclk_div2.hw },
367 { .hw = &g12a_fclk_div3.hw },
381 .hw.init = &(struct clk_init_data){
386 { .hw = &g12a_fclk_div2.hw },
387 { .hw = &g12a_fclk_div3.hw },
409 .hw.init = &(struct clk_init_data){
413 &g12a_cpu_clk_premux0.hw
428 .hw.init = &(struct clk_init_data){
432 &g12a_cpu_clk_premux0.hw,
433 &g12a_cpu_clk_mux0_div.hw,
447 .hw.init = &(struct clk_init_data){
451 &g12a_cpu_clk_premux1.hw
464 .hw.init = &(struct clk_init_data){
468 &g12a_cpu_clk_premux1.hw,
469 &g12a_cpu_clk_mux1_div.hw,
485 .hw.init = &(struct clk_init_data){
489 &g12a_cpu_clk_postmux0.hw,
490 &g12a_cpu_clk_postmux1.hw,
505 .hw.init = &(struct clk_init_data){
509 &g12a_cpu_clk_dyn.hw,
510 &g12a_sys_pll.hw,
525 .hw.init = &(struct clk_init_data){
529 &g12a_cpu_clk_dyn.hw,
530 &g12b_sys1_pll.hw
545 .hw.init = &(struct clk_init_data){
550 { .hw = &g12a_fclk_div2.hw },
551 { .hw = &g12a_fclk_div3.hw },
572 .hw.init = &(struct clk_init_data){
576 &g12b_cpub_clk_premux0.hw
591 .hw.init = &(struct clk_init_data){
595 &g12b_cpub_clk_premux0.hw,
596 &g12b_cpub_clk_mux0_div.hw
610 .hw.init = &(struct clk_init_data){
615 { .hw = &g12a_fclk_div2.hw },
616 { .hw = &g12a_fclk_div3.hw },
631 .hw.init = &(struct clk_init_data){
635 &g12b_cpub_clk_premux1.hw
648 .hw.init = &(struct clk_init_data){
652 &g12b_cpub_clk_premux1.hw,
653 &g12b_cpub_clk_mux1_div.hw
669 .hw.init = &(struct clk_init_data){
673 &g12b_cpub_clk_postmux0.hw,
674 &g12b_cpub_clk_postmux1.hw
689 .hw.init = &(struct clk_init_data){
693 &g12b_cpub_clk_dyn.hw,
694 &g12a_sys_pll.hw
710 .hw.init = &(struct clk_init_data){
715 { .hw = &g12a_fclk_div2.hw },
716 { .hw = &g12a_fclk_div3.hw },
717 { .hw = &sm1_gp1_pll.hw },
730 .hw.init = &(struct clk_init_data){
735 { .hw = &g12a_fclk_div2.hw },
736 { .hw = &g12a_fclk_div3.hw },
737 { .hw = &sm1_gp1_pll.hw },
750 .hw.init = &(struct clk_init_data){
754 &sm1_dsu_clk_premux0.hw
767 .hw.init = &(struct clk_init_data){
771 &sm1_dsu_clk_premux0.hw,
772 &sm1_dsu_clk_mux0_div.hw,
785 .hw.init = &(struct clk_init_data){
789 &sm1_dsu_clk_premux1.hw
802 .hw.init = &(struct clk_init_data){
806 &sm1_dsu_clk_premux1.hw,
807 &sm1_dsu_clk_mux1_div.hw,
820 .hw.init = &(struct clk_init_data){
824 &sm1_dsu_clk_postmux0.hw,
825 &sm1_dsu_clk_postmux1.hw,
838 .hw.init = &(struct clk_init_data){
842 &sm1_dsu_clk_dyn.hw,
843 &g12a_sys_pll.hw,
856 .hw.init = &(struct clk_init_data){
860 &g12a_cpu_clk.hw,
874 .hw.init = &(struct clk_init_data){
878 &g12a_cpu_clk.hw,
892 .hw.init = &(struct clk_init_data){
896 &g12a_cpu_clk.hw,
910 .hw.init = &(struct clk_init_data){
914 &g12a_cpu_clk.hw,
915 &sm1_dsu_final_clk.hw,
1027 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1028 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1029 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1030 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1035 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1036 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1037 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1038 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1110 .sys_pll = &g12a_sys_pll.hw,
1111 .cpu_clk = &g12a_cpu_clk.hw,
1112 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1118 .sys_pll = &g12b_sys1_pll.hw,
1119 .cpu_clk = &g12b_cpu_clk.hw,
1120 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1126 .sys_pll = &g12a_sys_pll.hw,
1127 .cpu_clk = &g12b_cpub_clk.hw,
1128 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1137 .hw.init = &(struct clk_init_data) {
1166 .hw.init = &(struct clk_init_data) {
1170 &g12b_cpub_clk.hw
1183 .hw.init = &(struct clk_init_data){
1187 &g12a_cpu_clk_div16_en.hw
1196 .hw.init = &(struct clk_init_data){
1200 &g12b_cpub_clk_div16_en.hw
1213 .hw.init = &(struct clk_init_data){
1229 .hw.init = &(struct clk_init_data) {
1233 &g12a_cpu_clk_apb_div.hw
1250 .hw.init = &(struct clk_init_data){
1266 .hw.init = &(struct clk_init_data) {
1270 &g12a_cpu_clk_atb_div.hw
1287 .hw.init = &(struct clk_init_data){
1303 .hw.init = &(struct clk_init_data) {
1307 &g12a_cpu_clk_axi_div.hw
1324 .hw.init = &(struct clk_init_data){
1340 .hw.init = &(struct clk_init_data) {
1344 &g12a_cpu_clk_trace_div.hw
1357 .hw.init = &(struct clk_init_data){
1361 &g12b_cpub_clk.hw
1370 .hw.init = &(struct clk_init_data){
1374 &g12b_cpub_clk.hw
1383 .hw.init = &(struct clk_init_data){
1387 &g12b_cpub_clk.hw
1396 .hw.init = &(struct clk_init_data){
1400 &g12b_cpub_clk.hw
1409 .hw.init = &(struct clk_init_data){
1413 &g12b_cpub_clk.hw
1422 .hw.init = &(struct clk_init_data){
1426 &g12b_cpub_clk.hw
1435 .hw.init = &(struct clk_init_data){
1439 &g12b_cpub_clk.hw
1453 .hw.init = &(struct clk_init_data){
1457 &g12b_cpub_clk_div2.hw,
1458 &g12b_cpub_clk_div3.hw,
1459 &g12b_cpub_clk_div4.hw,
1460 &g12b_cpub_clk_div5.hw,
1461 &g12b_cpub_clk_div6.hw,
1462 &g12b_cpub_clk_div7.hw,
1463 &g12b_cpub_clk_div8.hw
1475 .hw.init = &(struct clk_init_data) {
1479 &g12b_cpub_clk_apb_sel.hw
1496 .hw.init = &(struct clk_init_data){
1500 &g12b_cpub_clk_div2.hw,
1501 &g12b_cpub_clk_div3.hw,
1502 &g12b_cpub_clk_div4.hw,
1503 &g12b_cpub_clk_div5.hw,
1504 &g12b_cpub_clk_div6.hw,
1505 &g12b_cpub_clk_div7.hw,
1506 &g12b_cpub_clk_div8.hw
1518 .hw.init = &(struct clk_init_data) {
1522 &g12b_cpub_clk_atb_sel.hw
1539 .hw.init = &(struct clk_init_data){
1543 &g12b_cpub_clk_div2.hw,
1544 &g12b_cpub_clk_div3.hw,
1545 &g12b_cpub_clk_div4.hw,
1546 &g12b_cpub_clk_div5.hw,
1547 &g12b_cpub_clk_div6.hw,
1548 &g12b_cpub_clk_div7.hw,
1549 &g12b_cpub_clk_div8.hw
1561 .hw.init = &(struct clk_init_data) {
1565 &g12b_cpub_clk_axi_sel.hw
1582 .hw.init = &(struct clk_init_data){
1586 &g12b_cpub_clk_div2.hw,
1587 &g12b_cpub_clk_div3.hw,
1588 &g12b_cpub_clk_div4.hw,
1589 &g12b_cpub_clk_div5.hw,
1590 &g12b_cpub_clk_div6.hw,
1591 &g12b_cpub_clk_div7.hw,
1592 &g12b_cpub_clk_div8.hw
1604 .hw.init = &(struct clk_init_data) {
1608 &g12b_cpub_clk_trace_sel.hw
1671 .hw.init = &(struct clk_init_data){
1689 .hw.init = &(struct clk_init_data){
1693 &g12a_gp0_pll_dco.hw
1733 .hw.init = &(struct clk_init_data){
1753 .hw.init = &(struct clk_init_data){
1757 &sm1_gp1_pll_dco.hw
1812 .hw.init = &(struct clk_init_data){
1830 .hw.init = &(struct clk_init_data){
1834 &g12a_hifi_pll_dco.hw
1903 .hw.init = &(struct clk_init_data){
1916 .hw.init = &(struct clk_init_data){
1920 &g12a_pcie_pll_dco.hw
1936 .hw.init = &(struct clk_init_data){
1940 &g12a_pcie_pll_dco_div2.hw
1950 .hw.init = &(struct clk_init_data){
1954 &g12a_pcie_pll_od.hw
1994 .hw.init = &(struct clk_init_data){
2016 .hw.init = &(struct clk_init_data){
2020 &g12a_hdmi_pll_dco.hw
2034 .hw.init = &(struct clk_init_data){
2038 &g12a_hdmi_pll_od.hw
2052 .hw.init = &(struct clk_init_data){
2056 &g12a_hdmi_pll_od2.hw
2066 .hw.init = &(struct clk_init_data){
2069 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2079 .hw.init = &(struct clk_init_data){
2083 &g12a_fclk_div4_div.hw
2092 .hw.init = &(struct clk_init_data){
2095 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2105 .hw.init = &(struct clk_init_data){
2109 &g12a_fclk_div5_div.hw
2118 .hw.init = &(struct clk_init_data){
2121 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2131 .hw.init = &(struct clk_init_data){
2135 &g12a_fclk_div7_div.hw
2144 .hw.init = &(struct clk_init_data){
2148 &g12a_fixed_pll_dco.hw
2159 .hw.init = &(struct clk_init_data){
2163 &g12a_fclk_div2p5_div.hw
2172 .hw.init = &(struct clk_init_data){
2176 &g12a_fixed_pll_dco.hw
2188 .hw.init = &(struct clk_init_data){
2193 { .hw = &g12a_mpll_50m_div.hw },
2202 .hw.init = &(struct clk_init_data){
2206 &g12a_fixed_pll_dco.hw
2241 .hw.init = &(struct clk_init_data){
2245 &g12a_mpll_prediv.hw
2256 .hw.init = &(struct clk_init_data){
2259 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2294 .hw.init = &(struct clk_init_data){
2298 &g12a_mpll_prediv.hw
2309 .hw.init = &(struct clk_init_data){
2312 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2347 .hw.init = &(struct clk_init_data){
2351 &g12a_mpll_prediv.hw
2362 .hw.init = &(struct clk_init_data){
2365 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2400 .hw.init = &(struct clk_init_data){
2404 &g12a_mpll_prediv.hw
2415 .hw.init = &(struct clk_init_data){
2418 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2427 { .hw = &g12a_fclk_div7.hw },
2428 { .hw = &g12a_mpll1.hw },
2429 { .hw = &g12a_mpll2.hw },
2430 { .hw = &g12a_fclk_div4.hw },
2431 { .hw = &g12a_fclk_div3.hw },
2432 { .hw = &g12a_fclk_div5.hw },
2442 .hw.init = &(struct clk_init_data){
2456 .hw.init = &(struct clk_init_data){
2460 &g12a_mpeg_clk_sel.hw
2472 .hw.init = &(struct clk_init_data){
2476 &g12a_mpeg_clk_div.hw
2485 { .hw = &g12a_fclk_div2.hw },
2486 { .hw = &g12a_fclk_div3.hw },
2487 { .hw = &g12a_fclk_div5.hw },
2488 { .hw = &g12a_fclk_div7.hw },
2504 .hw.init = &(struct clk_init_data) {
2519 .hw.init = &(struct clk_init_data) {
2523 &g12a_sd_emmc_a_clk0_sel.hw
2535 .hw.init = &(struct clk_init_data){
2539 &g12a_sd_emmc_a_clk0_div.hw
2553 .hw.init = &(struct clk_init_data) {
2568 .hw.init = &(struct clk_init_data) {
2572 &g12a_sd_emmc_b_clk0_sel.hw
2584 .hw.init = &(struct clk_init_data){
2588 &g12a_sd_emmc_b_clk0_div.hw
2602 .hw.init = &(struct clk_init_data) {
2617 .hw.init = &(struct clk_init_data) {
2621 &g12a_sd_emmc_c_clk0_sel.hw
2633 .hw.init = &(struct clk_init_data){
2637 &g12a_sd_emmc_c_clk0_div.hw
2659 .hw.init = &(struct clk_init_data) {
2662 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2669 &g12a_vid_pll_div.hw,
2670 &g12a_hdmi_pll.hw,
2679 .hw.init = &(struct clk_init_data){
2697 .hw.init = &(struct clk_init_data) {
2701 &g12a_vid_pll_sel.hw
2711 &g12a_fclk_div3.hw,
2712 &g12a_fclk_div4.hw,
2713 &g12a_fclk_div5.hw,
2714 &g12a_fclk_div7.hw,
2715 &g12a_mpll1.hw,
2716 &g12a_vid_pll.hw,
2717 &g12a_hifi_pll.hw,
2718 &g12a_gp0_pll.hw,
2727 .hw.init = &(struct clk_init_data){
2742 .hw.init = &(struct clk_init_data){
2745 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2756 .hw.init = &(struct clk_init_data) {
2759 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2771 .hw.init = &(struct clk_init_data){
2786 .hw.init = &(struct clk_init_data){
2789 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2800 .hw.init = &(struct clk_init_data) {
2803 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2815 .hw.init = &(struct clk_init_data){
2823 &g12a_vpu_0.hw,
2824 &g12a_vpu_1.hw,
2834 &g12a_fclk_div2p5.hw,
2835 &g12a_fclk_div3.hw,
2836 &g12a_fclk_div4.hw,
2837 &g12a_fclk_div5.hw,
2838 &g12a_fclk_div7.hw,
2839 &g12a_hifi_pll.hw,
2840 &g12a_gp0_pll.hw,
2850 .hw.init = &(struct clk_init_data){
2866 .hw.init = &(struct clk_init_data){
2870 &g12a_vdec_1_sel.hw
2882 .hw.init = &(struct clk_init_data) {
2886 &g12a_vdec_1_div.hw
2900 .hw.init = &(struct clk_init_data){
2916 .hw.init = &(struct clk_init_data){
2920 &g12a_vdec_hevcf_sel.hw
2932 .hw.init = &(struct clk_init_data) {
2936 &g12a_vdec_hevcf_div.hw
2950 .hw.init = &(struct clk_init_data){
2966 .hw.init = &(struct clk_init_data){
2970 &g12a_vdec_hevc_sel.hw
2982 .hw.init = &(struct clk_init_data) {
2986 &g12a_vdec_hevc_div.hw
2996 &g12a_fclk_div4.hw,
2997 &g12a_fclk_div3.hw,
2998 &g12a_fclk_div5.hw,
2999 &g12a_fclk_div7.hw,
3000 &g12a_mpll1.hw,
3001 &g12a_vid_pll.hw,
3002 &g12a_mpll2.hw,
3003 &g12a_fclk_div2p5.hw,
3012 .hw.init = &(struct clk_init_data){
3027 .hw.init = &(struct clk_init_data){
3031 &g12a_vapb_0_sel.hw
3043 .hw.init = &(struct clk_init_data) {
3047 &g12a_vapb_0_div.hw
3060 .hw.init = &(struct clk_init_data){
3075 .hw.init = &(struct clk_init_data){
3079 &g12a_vapb_1_sel.hw
3091 .hw.init = &(struct clk_init_data) {
3095 &g12a_vapb_1_div.hw
3108 .hw.init = &(struct clk_init_data){
3116 &g12a_vapb_0.hw,
3117 &g12a_vapb_1.hw,
3129 .hw.init = &(struct clk_init_data) {
3132 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3139 &g12a_vid_pll.hw,
3140 &g12a_gp0_pll.hw,
3141 &g12a_hifi_pll.hw,
3142 &g12a_mpll1.hw,
3143 &g12a_fclk_div3.hw,
3144 &g12a_fclk_div4.hw,
3145 &g12a_fclk_div5.hw,
3146 &g12a_fclk_div7.hw,
3155 .hw.init = &(struct clk_init_data){
3170 .hw.init = &(struct clk_init_data){
3184 .hw.init = &(struct clk_init_data) {
3187 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3198 .hw.init = &(struct clk_init_data) {
3201 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3212 .hw.init = &(struct clk_init_data){
3216 &g12a_vclk_input.hw
3242 .hw.init = &(struct clk_init_data){
3246 &g12a_vclk2_input.hw
3258 .hw.init = &(struct clk_init_data) {
3261 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3280 .hw.init = &(struct clk_init_data) {
3283 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3294 .hw.init = &(struct clk_init_data) {
3297 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3308 .hw.init = &(struct clk_init_data) {
3311 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3322 .hw.init = &(struct clk_init_data) {
3325 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3336 .hw.init = &(struct clk_init_data) {
3339 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3350 .hw.init = &(struct clk_init_data) {
3353 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3364 .hw.init = &(struct clk_init_data) {
3367 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3378 .hw.init = &(struct clk_init_data) {
3381 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3392 .hw.init = &(struct clk_init_data) {
3395 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3406 .hw.init = &(struct clk_init_data) {
3409 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3420 .hw.init = &(struct clk_init_data) {
3423 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3432 .hw.init = &(struct clk_init_data){
3436 &g12a_vclk_div2_en.hw
3445 .hw.init = &(struct clk_init_data){
3449 &g12a_vclk_div4_en.hw
3458 .hw.init = &(struct clk_init_data){
3462 &g12a_vclk_div6_en.hw
3471 .hw.init = &(struct clk_init_data){
3475 &g12a_vclk_div12_en.hw
3484 .hw.init = &(struct clk_init_data){
3488 &g12a_vclk2_div2_en.hw
3498 .hw.init = &(struct clk_init_data){
3502 &g12a_vclk2_div4_en.hw
3512 .hw.init = &(struct clk_init_data){
3516 &g12a_vclk2_div6_en.hw
3526 .hw.init = &(struct clk_init_data){
3530 &g12a_vclk2_div12_en.hw
3539 &g12a_vclk_div1.hw,
3540 &g12a_vclk_div2.hw,
3541 &g12a_vclk_div4.hw,
3542 &g12a_vclk_div6.hw,
3543 &g12a_vclk_div12.hw,
3544 &g12a_vclk2_div1.hw,
3545 &g12a_vclk2_div2.hw,
3546 &g12a_vclk2_div4.hw,
3547 &g12a_vclk2_div6.hw,
3548 &g12a_vclk2_div12.hw,
3558 .hw.init = &(struct clk_init_data){
3574 .hw.init = &(struct clk_init_data){
3590 .hw.init = &(struct clk_init_data){
3606 .hw.init = &(struct clk_init_data){
3618 &g12a_vclk_div1.hw,
3619 &g12a_vclk_div2.hw,
3620 &g12a_vclk_div4.hw,
3621 &g12a_vclk_div6.hw,
3622 &g12a_vclk_div12.hw,
3623 &g12a_vclk2_div1.hw,
3624 &g12a_vclk2_div2.hw,
3625 &g12a_vclk2_div4.hw,
3626 &g12a_vclk2_div6.hw,
3627 &g12a_vclk2_div12.hw,
3637 .hw.init = &(struct clk_init_data){
3651 .hw.init = &(struct clk_init_data) {
3655 &g12a_cts_enci_sel.hw
3667 .hw.init = &(struct clk_init_data) {
3671 &g12a_cts_encp_sel.hw
3683 .hw.init = &(struct clk_init_data) {
3687 &g12a_cts_encl_sel.hw
3699 .hw.init = &(struct clk_init_data) {
3703 &g12a_cts_vdac_sel.hw
3715 .hw.init = &(struct clk_init_data) {
3719 &g12a_hdmi_tx_sel.hw
3729 &g12a_vid_pll.hw,
3730 &g12a_gp0_pll.hw,
3731 &g12a_hifi_pll.hw,
3732 &g12a_mpll1.hw,
3733 &g12a_fclk_div2.hw,
3734 &g12a_fclk_div2p5.hw,
3735 &g12a_fclk_div3.hw,
3736 &g12a_fclk_div7.hw,
3746 .hw.init = &(struct clk_init_data){
3772 .hw.init = &(struct clk_init_data){
3776 &g12a_mipi_dsi_pxclk_sel.hw
3788 .hw.init = &(struct clk_init_data) {
3792 &g12a_mipi_dsi_pxclk_div.hw
3803 { .hw = &g12a_gp0_pll.hw },
3804 { .hw = &g12a_hifi_pll.hw },
3805 { .hw = &g12a_fclk_div2p5.hw },
3806 { .hw = &g12a_fclk_div3.hw },
3807 { .hw = &g12a_fclk_div4.hw },
3808 { .hw = &g12a_fclk_div5.hw },
3809 { .hw = &g12a_fclk_div7.hw },
3818 .hw.init = &(struct clk_init_data){
3832 .hw.init = &(struct clk_init_data){
3836 &g12b_mipi_isp_sel.hw
3848 .hw.init = &(struct clk_init_data) {
3852 &g12b_mipi_isp_div.hw
3863 { .hw = &g12a_fclk_div4.hw },
3864 { .hw = &g12a_fclk_div3.hw },
3865 { .hw = &g12a_fclk_div5.hw },
3875 .hw.init = &(struct clk_init_data){
3890 .hw.init = &(struct clk_init_data){
3893 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3904 .hw.init = &(struct clk_init_data) {
3907 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3921 { .hw = &g12a_gp0_pll.hw },
3922 { .hw = &g12a_hifi_pll.hw },
3923 { .hw = &g12a_fclk_div2p5.hw },
3924 { .hw = &g12a_fclk_div3.hw },
3925 { .hw = &g12a_fclk_div4.hw },
3926 { .hw = &g12a_fclk_div5.hw },
3927 { .hw = &g12a_fclk_div7.hw },
3936 .hw.init = &(struct clk_init_data){
3957 .hw.init = &(struct clk_init_data){
3961 &g12a_mali_0_sel.hw
3973 .hw.init = &(struct clk_init_data){
3977 &g12a_mali_0_div.hw
3990 .hw.init = &(struct clk_init_data){
4011 .hw.init = &(struct clk_init_data){
4015 &g12a_mali_1_sel.hw
4027 .hw.init = &(struct clk_init_data){
4031 &g12a_mali_1_div.hw
4039 &g12a_mali_0.hw,
4040 &g12a_mali_1.hw,
4049 .hw.init = &(struct clk_init_data){
4064 .hw.init = &(struct clk_init_data){
4079 .hw.init = &(struct clk_init_data){
4083 &g12a_ts_div.hw
4093 { .hw = &g12a_clk81.hw },
4094 { .hw = &g12a_fclk_div4.hw },
4095 { .hw = &g12a_fclk_div3.hw },
4096 { .hw = &g12a_fclk_div5.hw },
4097 { .hw = &g12a_fclk_div7.hw },
4106 .hw.init = &(struct clk_init_data){
4120 .hw.init = &(struct clk_init_data){
4124 &g12a_spicc0_sclk_sel.hw
4136 .hw.init = &(struct clk_init_data){
4140 &g12a_spicc0_sclk_div.hw
4153 .hw.init = &(struct clk_init_data){
4167 .hw.init = &(struct clk_init_data){
4171 &g12a_spicc1_sclk_sel.hw
4183 .hw.init = &(struct clk_init_data){
4187 &g12a_spicc1_sclk_div.hw
4198 { .hw = &g12a_gp0_pll.hw, },
4199 { .hw = &g12a_hifi_pll.hw, },
4200 { .hw = &g12a_fclk_div2p5.hw, },
4201 { .hw = &g12a_fclk_div3.hw, },
4202 { .hw = &g12a_fclk_div4.hw, },
4203 { .hw = &g12a_fclk_div5.hw, },
4204 { .hw = &g12a_fclk_div7.hw },
4213 .hw.init = &(struct clk_init_data){
4227 .hw.init = &(struct clk_init_data){
4231 &sm1_nna_axi_clk_sel.hw
4243 .hw.init = &(struct clk_init_data){
4247 &sm1_nna_axi_clk_div.hw
4260 .hw.init = &(struct clk_init_data){
4274 .hw.init = &(struct clk_init_data){
4278 &sm1_nna_core_clk_sel.hw
4290 .hw.init = &(struct clk_init_data){
4294 &sm1_nna_core_clk_div.hw
4302 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4305 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4387 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4388 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4389 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4390 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4391 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4392 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4393 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4394 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4395 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4396 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4397 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4398 [CLKID_CLK81] = &g12a_clk81.hw,
4399 [CLKID_MPLL0] = &g12a_mpll0.hw,
4400 [CLKID_MPLL1] = &g12a_mpll1.hw,
4401 [CLKID_MPLL2] = &g12a_mpll2.hw,
4402 [CLKID_MPLL3] = &g12a_mpll3.hw,
4403 [CLKID_DDR] = &g12a_ddr.hw,
4404 [CLKID_DOS] = &g12a_dos.hw,
4405 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4406 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4407 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4408 [CLKID_ISA] = &g12a_isa.hw,
4409 [CLKID_PL301] = &g12a_pl301.hw,
4410 [CLKID_PERIPHS] = &g12a_periphs.hw,
4411 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4412 [CLKID_I2C] = &g12a_i2c.hw,
4413 [CLKID_SANA] = &g12a_sana.hw,
4414 [CLKID_SD] = &g12a_sd.hw,
4415 [CLKID_RNG0] = &g12a_rng0.hw,
4416 [CLKID_UART0] = &g12a_uart0.hw,
4417 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4418 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4419 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4420 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4421 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4422 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4423 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4424 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4425 [CLKID_AUDIO] = &g12a_audio.hw,
4426 [CLKID_ETH] = &g12a_eth_core.hw,
4427 [CLKID_DEMUX] = &g12a_demux.hw,
4428 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4429 [CLKID_ADC] = &g12a_adc.hw,
4430 [CLKID_UART1] = &g12a_uart1.hw,
4431 [CLKID_G2D] = &g12a_g2d.hw,
4432 [CLKID_RESET] = &g12a_reset.hw,
4433 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4434 [CLKID_PARSER] = &g12a_parser.hw,
4435 [CLKID_USB] = &g12a_usb_general.hw,
4436 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4437 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4438 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4439 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4440 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4441 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4442 [CLKID_BT656] = &g12a_bt656.hw,
4443 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4444 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4445 [CLKID_UART2] = &g12a_uart2.hw,
4446 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4447 [CLKID_GIC] = &g12a_gic.hw,
4448 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4449 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4450 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4451 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4452 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4453 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4454 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4455 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4456 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4457 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4458 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4459 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4460 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4461 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4462 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4463 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4464 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4465 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4466 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4467 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4468 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4469 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4470 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4471 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4472 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4473 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4474 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4475 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4476 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4477 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4478 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4479 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4480 [CLKID_ENC480P] = &g12a_enc480p.hw,
4481 [CLKID_RNG1] = &g12a_rng1.hw,
4482 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4483 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4484 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4485 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4486 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4487 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4488 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4489 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4490 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4491 [CLKID_DMA] = &g12a_dma.hw,
4492 [CLKID_EFUSE] = &g12a_efuse.hw,
4493 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4494 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4495 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4496 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4497 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4498 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4499 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4500 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4501 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4502 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4503 [CLKID_VPU] = &g12a_vpu.hw,
4504 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4505 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4506 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4507 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4508 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4509 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4510 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4511 [CLKID_VAPB] = &g12a_vapb.hw,
4512 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4513 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4514 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4515 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4516 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4517 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4518 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4519 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4520 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4521 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4522 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4523 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4524 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4525 [CLKID_VCLK] = &g12a_vclk.hw,
4526 [CLKID_VCLK2] = &g12a_vclk2.hw,
4527 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4528 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4529 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4530 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4531 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4532 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4533 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4534 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4535 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4536 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4537 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4538 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4539 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4540 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4541 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4542 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4543 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4544 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4545 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4546 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4547 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4548 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4549 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4550 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4551 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4552 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4553 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4554 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4555 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4556 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4557 [CLKID_HDMI] = &g12a_hdmi.hw,
4558 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4559 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4560 [CLKID_MALI_0] = &g12a_mali_0.hw,
4561 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4562 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4563 [CLKID_MALI_1] = &g12a_mali_1.hw,
4564 [CLKID_MALI] = &g12a_mali.hw,
4565 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4566 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4567 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4568 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4569 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4570 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4571 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4572 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4573 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4574 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4575 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4576 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4577 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4578 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4579 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4580 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4581 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4582 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4583 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4584 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4585 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4586 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4587 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4588 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4589 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4590 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4591 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4592 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4593 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4594 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4595 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4596 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4597 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4598 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4599 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4600 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4601 [CLKID_TS] = &g12a_ts.hw,
4602 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4603 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4604 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4605 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4606 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4607 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4608 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4609 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4610 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4614 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4615 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4616 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4617 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4618 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4619 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4620 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4621 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4622 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4623 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4624 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4625 [CLKID_CLK81] = &g12a_clk81.hw,
4626 [CLKID_MPLL0] = &g12a_mpll0.hw,
4627 [CLKID_MPLL1] = &g12a_mpll1.hw,
4628 [CLKID_MPLL2] = &g12a_mpll2.hw,
4629 [CLKID_MPLL3] = &g12a_mpll3.hw,
4630 [CLKID_DDR] = &g12a_ddr.hw,
4631 [CLKID_DOS] = &g12a_dos.hw,
4632 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4633 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4634 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4635 [CLKID_ISA] = &g12a_isa.hw,
4636 [CLKID_PL301] = &g12a_pl301.hw,
4637 [CLKID_PERIPHS] = &g12a_periphs.hw,
4638 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4639 [CLKID_I2C] = &g12a_i2c.hw,
4640 [CLKID_SANA] = &g12a_sana.hw,
4641 [CLKID_SD] = &g12a_sd.hw,
4642 [CLKID_RNG0] = &g12a_rng0.hw,
4643 [CLKID_UART0] = &g12a_uart0.hw,
4644 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4645 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4646 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4647 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4648 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4649 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4650 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4651 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4652 [CLKID_AUDIO] = &g12a_audio.hw,
4653 [CLKID_ETH] = &g12a_eth_core.hw,
4654 [CLKID_DEMUX] = &g12a_demux.hw,
4655 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4656 [CLKID_ADC] = &g12a_adc.hw,
4657 [CLKID_UART1] = &g12a_uart1.hw,
4658 [CLKID_G2D] = &g12a_g2d.hw,
4659 [CLKID_RESET] = &g12a_reset.hw,
4660 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4661 [CLKID_PARSER] = &g12a_parser.hw,
4662 [CLKID_USB] = &g12a_usb_general.hw,
4663 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4664 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4665 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4666 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4667 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4668 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4669 [CLKID_BT656] = &g12a_bt656.hw,
4670 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4671 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4672 [CLKID_UART2] = &g12a_uart2.hw,
4673 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4674 [CLKID_GIC] = &g12a_gic.hw,
4675 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4676 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4677 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4678 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4679 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4680 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4681 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4682 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4683 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4684 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4685 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4686 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4687 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4688 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4689 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4690 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4691 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4692 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4693 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4694 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4695 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4696 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4697 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4698 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4699 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4700 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4701 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4702 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4703 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4704 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4705 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4706 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4707 [CLKID_ENC480P] = &g12a_enc480p.hw,
4708 [CLKID_RNG1] = &g12a_rng1.hw,
4709 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4710 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4711 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4712 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4713 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4714 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4715 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4716 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4717 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4718 [CLKID_DMA] = &g12a_dma.hw,
4719 [CLKID_EFUSE] = &g12a_efuse.hw,
4720 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4721 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4722 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4723 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4724 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4725 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4726 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4727 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4728 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4729 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4730 [CLKID_VPU] = &g12a_vpu.hw,
4731 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4732 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4733 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4734 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4735 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4736 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4737 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4738 [CLKID_VAPB] = &g12a_vapb.hw,
4739 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4740 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4741 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4742 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4743 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4744 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4745 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4746 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4747 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4748 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4749 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4750 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4751 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4752 [CLKID_VCLK] = &g12a_vclk.hw,
4753 [CLKID_VCLK2] = &g12a_vclk2.hw,
4754 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4755 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4756 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4757 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4758 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4759 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4760 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4761 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4762 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4763 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4764 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4765 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4766 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4767 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4768 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4769 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4770 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4771 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4772 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4773 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4774 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4775 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4776 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4777 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4778 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4779 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4780 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4781 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4782 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4783 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4784 [CLKID_HDMI] = &g12a_hdmi.hw,
4785 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4786 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4787 [CLKID_MALI_0] = &g12a_mali_0.hw,
4788 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4789 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4790 [CLKID_MALI_1] = &g12a_mali_1.hw,
4791 [CLKID_MALI] = &g12a_mali.hw,
4792 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4793 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4794 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4795 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4796 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4797 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4798 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4799 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4800 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4801 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4802 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4803 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4804 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4805 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4806 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4807 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4808 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4809 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4810 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4811 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4812 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4813 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4814 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4815 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4816 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4817 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4818 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4819 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4820 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4821 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4822 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4823 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4824 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4825 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4826 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4827 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4828 [CLKID_TS] = &g12a_ts.hw,
4829 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4830 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4831 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4832 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4833 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4834 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4835 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4836 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4837 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4838 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4839 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4840 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4841 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4842 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4843 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4844 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4845 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4846 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4847 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4848 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4849 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4850 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4851 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4852 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4853 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4854 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4855 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4856 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4857 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4858 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4859 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4860 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4861 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4862 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4863 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4864 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4865 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4866 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4867 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4868 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4869 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
4870 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4871 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4872 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4873 [CLKID_MIPI_ISP_SEL] = &g12b_mipi_isp_sel.hw,
4874 [CLKID_MIPI_ISP_DIV] = &g12b_mipi_isp_div.hw,
4875 [CLKID_MIPI_ISP] = &g12b_mipi_isp.hw,
4876 [CLKID_MIPI_ISP_GATE] = &g12b_mipi_isp_gate.hw,
4877 [CLKID_MIPI_ISP_CSI_PHY0] = &g12b_csi_phy0.hw,
4878 [CLKID_MIPI_ISP_CSI_PHY1] = &g12b_csi_phy1.hw,
4882 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4883 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4884 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4885 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4886 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4887 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4888 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4889 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4890 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4891 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4892 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4893 [CLKID_CLK81] = &g12a_clk81.hw,
4894 [CLKID_MPLL0] = &g12a_mpll0.hw,
4895 [CLKID_MPLL1] = &g12a_mpll1.hw,
4896 [CLKID_MPLL2] = &g12a_mpll2.hw,
4897 [CLKID_MPLL3] = &g12a_mpll3.hw,
4898 [CLKID_DDR] = &g12a_ddr.hw,
4899 [CLKID_DOS] = &g12a_dos.hw,
4900 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4901 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4902 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4903 [CLKID_ISA] = &g12a_isa.hw,
4904 [CLKID_PL301] = &g12a_pl301.hw,
4905 [CLKID_PERIPHS] = &g12a_periphs.hw,
4906 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4907 [CLKID_I2C] = &g12a_i2c.hw,
4908 [CLKID_SANA] = &g12a_sana.hw,
4909 [CLKID_SD] = &g12a_sd.hw,
4910 [CLKID_RNG0] = &g12a_rng0.hw,
4911 [CLKID_UART0] = &g12a_uart0.hw,
4912 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4913 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4914 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4915 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4916 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4917 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4918 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4919 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4920 [CLKID_AUDIO] = &g12a_audio.hw,
4921 [CLKID_ETH] = &g12a_eth_core.hw,
4922 [CLKID_DEMUX] = &g12a_demux.hw,
4923 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4924 [CLKID_ADC] = &g12a_adc.hw,
4925 [CLKID_UART1] = &g12a_uart1.hw,
4926 [CLKID_G2D] = &g12a_g2d.hw,
4927 [CLKID_RESET] = &g12a_reset.hw,
4928 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4929 [CLKID_PARSER] = &g12a_parser.hw,
4930 [CLKID_USB] = &g12a_usb_general.hw,
4931 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4932 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4933 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4934 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4935 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4936 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4937 [CLKID_BT656] = &g12a_bt656.hw,
4938 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4939 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4940 [CLKID_UART2] = &g12a_uart2.hw,
4941 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4942 [CLKID_GIC] = &g12a_gic.hw,
4943 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4944 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4945 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4946 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4947 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4948 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4949 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4950 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4951 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4952 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4953 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4954 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4955 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4956 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4957 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4958 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4959 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4960 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4961 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4962 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4963 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4964 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4965 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4966 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4967 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4968 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4969 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4970 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4971 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4972 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4973 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4974 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4975 [CLKID_ENC480P] = &g12a_enc480p.hw,
4976 [CLKID_RNG1] = &g12a_rng1.hw,
4977 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4978 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4979 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4980 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4981 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4982 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4983 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4984 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4985 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4986 [CLKID_DMA] = &g12a_dma.hw,
4987 [CLKID_EFUSE] = &g12a_efuse.hw,
4988 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4989 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4990 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4991 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4992 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4993 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4994 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4995 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4996 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4997 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4998 [CLKID_VPU] = &g12a_vpu.hw,
4999 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
5000 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
5001 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
5002 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
5003 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
5004 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
5005 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
5006 [CLKID_VAPB] = &g12a_vapb.hw,
5007 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
5008 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
5009 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
5010 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
5011 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
5012 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
5013 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
5014 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
5015 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
5016 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
5017 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
5018 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
5019 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
5020 [CLKID_VCLK] = &g12a_vclk.hw,
5021 [CLKID_VCLK2] = &g12a_vclk2.hw,
5022 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
5023 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
5024 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
5025 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
5026 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
5027 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
5028 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
5029 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
5030 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
5031 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
5032 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
5033 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
5034 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
5035 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
5036 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
5037 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
5038 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
5039 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
5040 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
5041 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
5042 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
5043 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
5044 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
5045 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
5046 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
5047 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
5048 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
5049 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
5050 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
5051 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
5052 [CLKID_HDMI] = &g12a_hdmi.hw,
5053 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
5054 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
5055 [CLKID_MALI_0] = &g12a_mali_0.hw,
5056 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
5057 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
5058 [CLKID_MALI_1] = &g12a_mali_1.hw,
5059 [CLKID_MALI] = &g12a_mali.hw,
5060 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
5061 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
5062 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
5063 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
5064 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
5065 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
5066 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
5067 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
5068 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
5069 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
5070 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
5071 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
5072 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
5073 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
5074 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
5075 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
5076 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
5077 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
5078 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
5079 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
5080 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
5081 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
5082 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
5083 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
5084 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
5085 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
5086 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
5087 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
5088 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
5089 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
5090 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
5091 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
5092 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
5093 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
5094 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
5095 [CLKID_TS_DIV] = &g12a_ts_div.hw,
5096 [CLKID_TS] = &g12a_ts.hw,
5097 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
5098 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
5099 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
5100 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
5101 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
5102 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
5103 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
5104 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
5105 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
5106 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
5107 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
5108 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
5109 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
5110 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
5111 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
5112 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
5113 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
5114 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
5115 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
5116 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
5117 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
5118 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
5119 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
5120 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
5121 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
5122 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
5123 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
5124 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
5125 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
5400 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw, in meson_g12a_dvfs_setup_common()
5410 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw, in meson_g12a_dvfs_setup_common()
5437 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw, in meson_g12b_dvfs_setup()
5447 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw, in meson_g12b_dvfs_setup()
5460 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw, in meson_g12b_dvfs_setup()
5470 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs"); in meson_g12b_dvfs_setup()
5479 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID); in meson_g12b_dvfs_setup()
5488 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID); in meson_g12b_dvfs_setup()
5511 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID); in meson_g12a_dvfs_setup()
5520 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID); in meson_g12a_dvfs_setup()