Lines Matching +full:0 +full:x12
11 #define APMU_CLK_GATE_CTRL 0x40
12 #define APMU_CCIC1 0x24
13 #define APMU_ISP 0x38
14 #define APMU_DSI1 0x44
15 #define APMU_DISP1 0x4c
16 #define APMU_CCIC0 0x50
17 #define APMU_SDH0 0x54
18 #define APMU_SDH1 0x58
19 #define APMU_USB 0x5c
20 #define APMU_NF 0x60
21 #define APMU_VPU 0xa4
22 #define APMU_GC 0xcc
23 #define APMU_SDH2 0xe0
24 #define APMU_GC2D 0xf4
25 #define APMU_TRACE 0x108
26 #define APMU_DVC_DFC_DEBUG 0x140
37 {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock},
38 {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock},
39 {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock},
40 {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock},
41 …{PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lo…
55 {PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL},
56 …h0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock},
57 …h1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock},
58 …dh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock}
93 pxa_unit->base = devm_platform_ioremap_resource(pdev, 0); in pxa1908_apmu_probe()
101 return 0; in pxa1908_apmu_probe()