Lines Matching +full:0 +full:x37000
53 .offset = 0x0,
56 .enable_reg = 0x62018,
57 .enable_mask = BIT(0),
70 { 0x1, 2 },
75 .offset = 0x0,
92 .offset = 0x1000,
95 .enable_reg = 0x62018,
109 .offset = 0x4000,
112 .enable_reg = 0x62018,
126 .offset = 0x5000,
129 .enable_reg = 0x62018,
143 .offset = 0x7000,
146 .enable_reg = 0x62018,
160 .offset = 0x9000,
163 .enable_reg = 0x62018,
177 { 0x1, 2 },
182 .offset = 0x9000,
199 { P_BI_TCXO, 0 },
211 { P_BI_TCXO, 0 },
225 { P_BI_TCXO, 0 },
245 { P_BI_TCXO, 0 },
255 { P_BI_TCXO, 0 },
269 { P_BI_TCXO, 0 },
283 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
293 .reg = 0x7b070,
307 .reg = 0x9d06c,
321 .reg = 0x4906c,
322 .shift = 0,
336 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
337 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
338 F(426400000, P_GCC_GPLL1_OUT_MAIN, 2.5, 0, 0),
339 F(500000000, P_GCC_GPLL7_OUT_MAIN, 1, 0, 0),
344 .cmd_rcgr = 0x70004,
345 .mnd_width = 0,
358 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
359 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
360 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
365 .cmd_rcgr = 0x74004,
379 .cmd_rcgr = 0x75004,
393 .cmd_rcgr = 0x76004,
407 F(19200000, P_BI_TCXO, 1, 0, 0),
412 .cmd_rcgr = 0x7b074,
426 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
431 .cmd_rcgr = 0x7b058,
432 .mnd_width = 0,
445 .cmd_rcgr = 0x9d070,
459 .cmd_rcgr = 0x9d054,
460 .mnd_width = 0,
473 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
478 .cmd_rcgr = 0x43010,
479 .mnd_width = 0,
494 F(19200000, P_BI_TCXO, 1, 0, 0),
499 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
502 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
506 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
518 .cmd_rcgr = 0x28018,
529 F(19200000, P_BI_TCXO, 1, 0, 0),
534 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
537 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
549 .cmd_rcgr = 0x28150,
565 .cmd_rcgr = 0x28288,
581 .cmd_rcgr = 0x283c0,
597 .cmd_rcgr = 0x284f8,
613 .cmd_rcgr = 0x28630,
629 .cmd_rcgr = 0x2e018,
645 .cmd_rcgr = 0x2e150,
661 .cmd_rcgr = 0x2e288,
677 .cmd_rcgr = 0x2e3c0,
693 .cmd_rcgr = 0x2e4f8,
709 .cmd_rcgr = 0x2e630,
721 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
722 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
723 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
724 F(192000000, P_GCC_GPLL9_OUT_EVEN, 2, 0, 0),
725 F(384000000, P_GCC_GPLL9_OUT_EVEN, 1, 0, 0),
730 .cmd_rcgr = 0x26018,
744 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
745 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
746 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
751 .cmd_rcgr = 0x2603c,
752 .mnd_width = 0,
765 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
766 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
767 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
772 .cmd_rcgr = 0x4902c,
786 .cmd_rcgr = 0x49044,
787 .mnd_width = 0,
800 .cmd_rcgr = 0x49070,
801 .mnd_width = 0,
814 .reg = 0x4905c,
815 .shift = 0,
829 .halt_reg = 0x7b094,
831 .hwcg_reg = 0x7b094,
834 .enable_reg = 0x62000,
844 .halt_reg = 0x4908c,
846 .hwcg_reg = 0x4908c,
849 .enable_reg = 0x4908c,
850 .enable_mask = BIT(0),
864 .halt_reg = 0x48004,
866 .hwcg_reg = 0x48004,
869 .enable_reg = 0x62000,
879 .halt_reg = 0x20034,
881 .hwcg_reg = 0x20034,
884 .enable_reg = 0x62000,
894 .halt_reg = 0x49088,
896 .hwcg_reg = 0x49088,
899 .enable_reg = 0x49088,
900 .enable_mask = BIT(0),
914 .halt_reg = 0x81154,
916 .hwcg_reg = 0x81154,
919 .enable_reg = 0x81154,
920 .enable_mask = BIT(0),
929 .halt_reg = 0x9d098,
931 .hwcg_reg = 0x9d098,
934 .enable_reg = 0x62000,
944 .halt_reg = 0x70000,
946 .hwcg_reg = 0x70000,
949 .enable_reg = 0x70000,
950 .enable_mask = BIT(0),
964 .halt_reg = 0x37008,
966 .hwcg_reg = 0x37008,
969 .enable_reg = 0x37008,
970 .enable_mask = BIT(0),
979 .halt_reg = 0x74000,
982 .enable_reg = 0x74000,
983 .enable_mask = BIT(0),
997 .halt_reg = 0x75000,
1000 .enable_reg = 0x75000,
1001 .enable_mask = BIT(0),
1015 .halt_reg = 0x76000,
1018 .enable_reg = 0x76000,
1019 .enable_mask = BIT(0),
1035 .enable_reg = 0x62000,
1052 .enable_reg = 0x62000,
1067 .halt_reg = 0x9b010,
1069 .hwcg_reg = 0x9b010,
1072 .enable_reg = 0x9b010,
1073 .enable_mask = BIT(0),
1082 .halt_reg = 0x9b018,
1085 .enable_reg = 0x9b018,
1086 .enable_mask = BIT(0),
1095 .halt_reg = 0x42030,
1097 .hwcg_reg = 0x42030,
1100 .enable_reg = 0x42030,
1101 .enable_mask = BIT(0),
1110 .halt_reg = 0x70020,
1112 .hwcg_reg = 0x70020,
1115 .enable_reg = 0x70020,
1116 .enable_mask = BIT(0),
1130 .halt_reg = 0x7b03c,
1133 .enable_reg = 0x62008,
1148 .halt_reg = 0x7b038,
1150 .hwcg_reg = 0x7b038,
1153 .enable_reg = 0x62008,
1163 .halt_reg = 0x7b02c,
1165 .hwcg_reg = 0x7b02c,
1168 .enable_reg = 0x62008,
1178 .halt_reg = 0x7b054,
1181 .enable_reg = 0x62000,
1196 .halt_reg = 0x7b048,
1199 .enable_reg = 0x62008,
1214 .halt_reg = 0x7b020,
1216 .hwcg_reg = 0x7b020,
1219 .enable_reg = 0x62008,
1220 .enable_mask = BIT(0),
1229 .halt_reg = 0x7b01c,
1232 .enable_reg = 0x62008,
1242 .halt_reg = 0x9d038,
1245 .enable_reg = 0x62000,
1260 .halt_reg = 0x9d034,
1262 .hwcg_reg = 0x9d034,
1265 .enable_reg = 0x62000,
1275 .halt_reg = 0x9d028,
1277 .hwcg_reg = 0x9d028,
1280 .enable_reg = 0x62000,
1290 .halt_reg = 0x9d050,
1293 .enable_reg = 0x62000,
1308 .halt_reg = 0x9d044,
1311 .enable_reg = 0x62000,
1326 .halt_reg = 0x9d01c,
1328 .hwcg_reg = 0x9d01c,
1331 .enable_reg = 0x62000,
1341 .halt_reg = 0x9d018,
1344 .enable_reg = 0x62000,
1354 .halt_reg = 0x4300c,
1357 .enable_reg = 0x4300c,
1358 .enable_mask = BIT(0),
1372 .halt_reg = 0x43004,
1374 .hwcg_reg = 0x43004,
1377 .enable_reg = 0x43004,
1378 .enable_mask = BIT(0),
1387 .halt_reg = 0x43008,
1390 .enable_reg = 0x43008,
1391 .enable_mask = BIT(0),
1400 .halt_reg = 0x9b008,
1402 .hwcg_reg = 0x9b008,
1405 .enable_reg = 0x9b008,
1406 .enable_mask = BIT(0),
1415 .halt_reg = 0x7b018,
1417 .hwcg_reg = 0x7b018,
1420 .enable_reg = 0x62000,
1430 .halt_reg = 0x42014,
1432 .hwcg_reg = 0x42014,
1435 .enable_reg = 0x42014,
1436 .enable_mask = BIT(0),
1445 .halt_reg = 0x42008,
1447 .hwcg_reg = 0x42008,
1450 .enable_reg = 0x42008,
1451 .enable_mask = BIT(0),
1460 .halt_reg = 0x4204c,
1462 .hwcg_reg = 0x4204c,
1465 .enable_reg = 0x4204c,
1466 .enable_mask = BIT(0),
1475 .halt_reg = 0x42010,
1477 .hwcg_reg = 0x42010,
1480 .enable_reg = 0x42010,
1481 .enable_mask = BIT(0),
1490 .halt_reg = 0x4200c,
1492 .hwcg_reg = 0x4200c,
1495 .enable_reg = 0x4200c,
1496 .enable_mask = BIT(0),
1505 .halt_reg = 0x33034,
1508 .enable_reg = 0x62008,
1518 .halt_reg = 0x33024,
1521 .enable_reg = 0x62008,
1531 .halt_reg = 0x2800c,
1534 .enable_reg = 0x62008,
1549 .halt_reg = 0x28144,
1552 .enable_reg = 0x62008,
1567 .halt_reg = 0x2827c,
1570 .enable_reg = 0x62008,
1585 .halt_reg = 0x283b4,
1588 .enable_reg = 0x62008,
1603 .halt_reg = 0x284ec,
1606 .enable_reg = 0x62008,
1621 .halt_reg = 0x28624,
1624 .enable_reg = 0x62008,
1639 .halt_reg = 0x3317c,
1642 .enable_reg = 0x62010,
1652 .halt_reg = 0x3316c,
1655 .enable_reg = 0x62010,
1656 .enable_mask = BIT(0),
1665 .halt_reg = 0x2e00c,
1668 .enable_reg = 0x62010,
1683 .halt_reg = 0x2e144,
1686 .enable_reg = 0x62010,
1701 .halt_reg = 0x2e27c,
1704 .enable_reg = 0x62010,
1719 .halt_reg = 0x2e3b4,
1722 .enable_reg = 0x62010,
1737 .halt_reg = 0x2e4ec,
1740 .enable_reg = 0x62010,
1755 .halt_reg = 0x2e624,
1758 .enable_reg = 0x62010,
1773 .halt_reg = 0x28004,
1775 .hwcg_reg = 0x28004,
1778 .enable_reg = 0x62008,
1788 .halt_reg = 0x28008,
1790 .hwcg_reg = 0x28008,
1793 .enable_reg = 0x62008,
1803 .halt_reg = 0x2e004,
1805 .hwcg_reg = 0x2e004,
1808 .enable_reg = 0x62010,
1818 .halt_reg = 0x2e008,
1820 .hwcg_reg = 0x2e008,
1823 .enable_reg = 0x62010,
1833 .halt_reg = 0x26010,
1836 .enable_reg = 0x26010,
1837 .enable_mask = BIT(0),
1846 .halt_reg = 0x26004,
1849 .enable_reg = 0x26004,
1850 .enable_mask = BIT(0),
1864 .halt_reg = 0x26030,
1866 .hwcg_reg = 0x26030,
1869 .enable_reg = 0x26030,
1870 .enable_mask = BIT(0),
1884 .halt_reg = 0x49018,
1887 .enable_reg = 0x49018,
1888 .enable_mask = BIT(0),
1902 .halt_reg = 0x49028,
1905 .enable_reg = 0x49028,
1906 .enable_mask = BIT(0),
1920 .halt_reg = 0x49024,
1923 .enable_reg = 0x49024,
1924 .enable_mask = BIT(0),
1933 .halt_reg = 0x49060,
1936 .enable_reg = 0x49060,
1937 .enable_mask = BIT(0),
1951 .halt_reg = 0x49064,
1954 .enable_reg = 0x49064,
1955 .enable_mask = BIT(0),
1969 .halt_reg = 0x49068,
1971 .hwcg_reg = 0x49068,
1974 .enable_reg = 0x49068,
1975 .enable_mask = BIT(0),
1989 .halt_reg = 0x42018,
1991 .hwcg_reg = 0x42018,
1994 .enable_reg = 0x42018,
1995 .enable_mask = BIT(0),
2004 .halt_reg = 0x42024,
2006 .hwcg_reg = 0x42024,
2009 .enable_reg = 0x42024,
2010 .enable_mask = BIT(0),
2019 .gdscr = 0x8d204,
2028 .gdscr = 0x8d054,
2037 .gdscr = 0x8d05c,
2046 .gdscr = 0x8d060,
2055 .gdscr = 0x7b004,
2056 .collapse_ctrl = 0x62200,
2057 .collapse_mask = BIT(0),
2066 .gdscr = 0x7c000,
2067 .collapse_ctrl = 0x62200,
2077 .gdscr = 0x9d004,
2078 .collapse_ctrl = 0x62200,
2088 .gdscr = 0x9e000,
2089 .collapse_ctrl = 0x62200,
2099 .gdscr = 0x49004,
2108 .gdscr = 0x60018,
2231 [GCC_DISPLAY_BCR] = { 0x37000 },
2232 [GCC_GPU_BCR] = { 0x9b000 },
2233 [GCC_PCIE_0_BCR] = { 0x7b000 },
2234 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
2235 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
2236 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
2237 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
2238 [GCC_PCIE_1_BCR] = { 0x9d000 },
2239 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
2240 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
2241 [GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
2242 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e024 },
2243 [GCC_PCIE_PHY_BCR] = { 0x7f000 },
2244 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
2245 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
2246 [GCC_PDM_BCR] = { 0x43000 },
2247 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x28000 },
2248 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x2e000 },
2249 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
2250 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
2251 [GCC_SDCC1_BCR] = { 0x26000 },
2252 [GCC_USB30_PRIM_BCR] = { 0x49000 },
2253 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
2254 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
2255 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
2256 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
2257 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
2258 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
2259 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
2260 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42024, .bit = 2, .udelay = 1000 },
2261 [GCC_VIDEO_BCR] = { 0x42000 },
2262 [GCC_IRIS_SS_HF_AXI_CLK_ARES] = { .reg = 0x42030, .bit = 2 },
2263 [GCC_IRIS_SS_SPD_AXI_CLK_ARES] = { .reg = 0x70020, .bit = 2 },
2264 [GCC_DDRSS_SPAD_CLK_ARES] = { .reg = 0x70000, .bit = 2 },
2299 .max_register = 0x1f1030,
2334 qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ in gcc_sar2130p_probe()
2335 qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ in gcc_sar2130p_probe()
2336 qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ in gcc_sar2130p_probe()
2337 qcom_branch_set_clk_en(regmap, 0x9b004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sar2130p_probe()
2340 regmap_write(regmap, 0x62204, 0x0); in gcc_sar2130p_probe()