Lines Matching +full:0 +full:x29000
52 .offset = 0x0,
55 .enable_reg = 0x52030,
56 .enable_mask = BIT(0),
69 { 0x1, 2 },
74 .offset = 0x0,
91 .offset = 0x4000,
94 .enable_reg = 0x52030,
108 .offset = 0x7000,
111 .enable_reg = 0x52030,
125 .offset = 0x8000,
128 .enable_reg = 0x52030,
142 .offset = 0x9000,
145 .enable_reg = 0x52030,
159 { P_BI_TCXO, 0 },
171 { P_BI_TCXO, 0 },
181 { P_BI_TCXO, 0 },
195 { P_BI_TCXO, 0 },
203 { P_BI_TCXO, 0 },
217 { P_BI_TCXO, 0 },
231 { P_BI_TCXO, 0 },
243 { P_BI_TCXO, 0 },
257 { P_BI_TCXO, 0 },
271 { P_BI_TCXO, 0 },
284 { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
294 { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
304 { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
317 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
318 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
319 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
324 .cmd_rcgr = 0x64004,
339 .cmd_rcgr = 0x65004,
354 .cmd_rcgr = 0x66004,
369 F(19200000, P_BI_TCXO, 1, 0, 0),
374 .cmd_rcgr = 0xa0180,
389 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
394 .cmd_rcgr = 0xa0054,
395 .mnd_width = 0,
409 .cmd_rcgr = 0x2c180,
424 .cmd_rcgr = 0x2c054,
425 .mnd_width = 0,
439 .cmd_rcgr = 0x13180,
454 .cmd_rcgr = 0x13054,
455 .mnd_width = 0,
469 .cmd_rcgr = 0x5808c,
484 .cmd_rcgr = 0x58070,
485 .mnd_width = 0,
499 .cmd_rcgr = 0x6b080,
514 .cmd_rcgr = 0x6b064,
515 .mnd_width = 0,
529 .cmd_rcgr = 0x2f080,
544 .cmd_rcgr = 0x2f064,
545 .mnd_width = 0,
559 .cmd_rcgr = 0x3108c,
574 .cmd_rcgr = 0x31070,
575 .mnd_width = 0,
589 .cmd_rcgr = 0x8d08c,
604 .cmd_rcgr = 0x8d070,
605 .mnd_width = 0,
619 .cmd_rcgr = 0xa400c,
620 .mnd_width = 0,
634 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
639 .cmd_rcgr = 0x33010,
640 .mnd_width = 0,
656 F(19200000, P_BI_TCXO, 1, 0, 0),
661 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
664 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
677 .cmd_rcgr = 0x42010,
694 .cmd_rcgr = 0x42148,
705 F(19200000, P_BI_TCXO, 1, 0, 0),
712 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
713 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
726 .cmd_rcgr = 0x42288,
743 .cmd_rcgr = 0x423c8,
754 F(19200000, P_BI_TCXO, 1, 0, 0),
759 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
762 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
775 .cmd_rcgr = 0x42500,
792 .cmd_rcgr = 0x42638,
809 .cmd_rcgr = 0x42770,
826 .cmd_rcgr = 0x428a8,
843 .cmd_rcgr = 0x18010,
860 .cmd_rcgr = 0x18148,
877 .cmd_rcgr = 0x18288,
894 .cmd_rcgr = 0x183c8,
911 .cmd_rcgr = 0x18500,
928 .cmd_rcgr = 0x18638,
945 .cmd_rcgr = 0x18770,
962 .cmd_rcgr = 0x188a8,
979 .cmd_rcgr = 0x1e010,
996 .cmd_rcgr = 0x1e148,
1013 .cmd_rcgr = 0x1e288,
1030 .cmd_rcgr = 0x1e3c8,
1047 .cmd_rcgr = 0x1e500,
1064 .cmd_rcgr = 0x1e638,
1081 .cmd_rcgr = 0x1e770,
1098 .cmd_rcgr = 0x1e8a8,
1108 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1109 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1110 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1111 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1116 .cmd_rcgr = 0x14018,
1132 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1133 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1138 .cmd_rcgr = 0x16018,
1153 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1154 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1155 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1156 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1161 .cmd_rcgr = 0x77030,
1176 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1177 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1178 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1183 .cmd_rcgr = 0x77080,
1184 .mnd_width = 0,
1198 .cmd_rcgr = 0x770b4,
1199 .mnd_width = 0,
1213 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1214 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1215 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1220 .cmd_rcgr = 0x77098,
1221 .mnd_width = 0,
1235 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1236 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1241 .cmd_rcgr = 0x2902c,
1256 .cmd_rcgr = 0x29158,
1257 .mnd_width = 0,
1271 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1272 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1273 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1274 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1279 .cmd_rcgr = 0x1702c,
1294 .cmd_rcgr = 0x17158,
1295 .mnd_width = 0,
1309 .cmd_rcgr = 0x3902c,
1324 .cmd_rcgr = 0x39044,
1325 .mnd_width = 0,
1339 .cmd_rcgr = 0xa102c,
1354 .cmd_rcgr = 0xa1044,
1355 .mnd_width = 0,
1369 .cmd_rcgr = 0xa202c,
1384 .cmd_rcgr = 0xa2044,
1385 .mnd_width = 0,
1399 .cmd_rcgr = 0x172a0,
1400 .mnd_width = 0,
1414 .cmd_rcgr = 0x39074,
1415 .mnd_width = 0,
1429 .cmd_rcgr = 0xa1074,
1430 .mnd_width = 0,
1444 .cmd_rcgr = 0xa2074,
1445 .mnd_width = 0,
1459 F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
1460 F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
1461 F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
1466 .cmd_rcgr = 0x9f024,
1481 F(19200000, P_BI_TCXO, 1, 0, 0),
1482 F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
1483 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1488 .cmd_rcgr = 0x9f0e8,
1489 .mnd_width = 0,
1503 .cmd_rcgr = 0x9f08c,
1504 .mnd_width = 0,
1518 F(19200000, P_BI_TCXO, 1, 0, 0),
1519 F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1524 .cmd_rcgr = 0x9f070,
1525 .mnd_width = 0,
1539 .cmd_rcgr = 0x2b024,
1554 .cmd_rcgr = 0x2b0e8,
1555 .mnd_width = 0,
1569 .cmd_rcgr = 0x2b08c,
1570 .mnd_width = 0,
1584 .cmd_rcgr = 0x2b070,
1585 .mnd_width = 0,
1599 .cmd_rcgr = 0x11024,
1614 .cmd_rcgr = 0x110e8,
1615 .mnd_width = 0,
1629 .cmd_rcgr = 0x1108c,
1630 .mnd_width = 0,
1644 .cmd_rcgr = 0x11070,
1645 .mnd_width = 0,
1659 .reg = 0x58088,
1673 .reg = 0x5806c,
1674 .shift = 0,
1687 .reg = 0x6b07c,
1701 .reg = 0x6b060,
1702 .shift = 0,
1715 .reg = 0x2f07c,
1729 .reg = 0x2f060,
1730 .shift = 0,
1743 .reg = 0x31088,
1757 .reg = 0x3106c,
1758 .shift = 0,
1771 .reg = 0x8d088,
1785 .reg = 0x8d06c,
1786 .shift = 0,
1799 .reg = 0x42284,
1800 .shift = 0,
1814 .reg = 0x423c4,
1815 .shift = 0,
1829 .reg = 0x18284,
1830 .shift = 0,
1844 .reg = 0x183c4,
1845 .shift = 0,
1859 .reg = 0x1e284,
1860 .shift = 0,
1874 .reg = 0x1e3c4,
1875 .shift = 0,
1889 .reg = 0x29284,
1890 .shift = 0,
1904 .reg = 0x17284,
1905 .shift = 0,
1919 .reg = 0x3905c,
1920 .shift = 0,
1934 .reg = 0xa105c,
1935 .shift = 0,
1949 .reg = 0xa205c,
1950 .shift = 0,
1964 .halt_reg = 0x2d17c,
1966 .hwcg_reg = 0x2d17c,
1969 .enable_reg = 0x2d17c,
1970 .enable_mask = BIT(0),
1979 .halt_reg = 0x2d174,
1981 .hwcg_reg = 0x2d174,
1984 .enable_reg = 0x2d174,
1985 .enable_mask = BIT(0),
1994 .halt_reg = 0x770e4,
1996 .hwcg_reg = 0x770e4,
1999 .enable_reg = 0x770e4,
2000 .enable_mask = BIT(0),
2014 .halt_reg = 0x2928c,
2016 .hwcg_reg = 0x2928c,
2019 .enable_reg = 0x2928c,
2020 .enable_mask = BIT(0),
2034 .halt_reg = 0x173d0,
2036 .hwcg_reg = 0x173d0,
2039 .enable_reg = 0x173d0,
2040 .enable_mask = BIT(0),
2054 .halt_reg = 0x39090,
2056 .hwcg_reg = 0x39090,
2059 .enable_reg = 0x39090,
2060 .enable_mask = BIT(0),
2074 .halt_reg = 0xa1090,
2076 .hwcg_reg = 0xa1090,
2079 .enable_reg = 0xa1090,
2080 .enable_mask = BIT(0),
2094 .halt_reg = 0xa2090,
2096 .hwcg_reg = 0xa2090,
2099 .enable_reg = 0xa2090,
2100 .enable_mask = BIT(0),
2114 .halt_reg = 0x9f118,
2116 .hwcg_reg = 0x9f118,
2119 .enable_reg = 0x9f118,
2120 .enable_mask = BIT(0),
2134 .halt_reg = 0x2b118,
2136 .hwcg_reg = 0x2b118,
2139 .enable_reg = 0x2b118,
2140 .enable_mask = BIT(0),
2154 .halt_reg = 0x11118,
2156 .hwcg_reg = 0x11118,
2159 .enable_reg = 0x11118,
2160 .enable_mask = BIT(0),
2174 .halt_reg = 0x2d034,
2176 .hwcg_reg = 0x2d034,
2179 .enable_reg = 0x2d034,
2180 .enable_mask = BIT(0),
2189 .halt_reg = 0x4a004,
2191 .hwcg_reg = 0x4a004,
2194 .enable_reg = 0x4a004,
2195 .enable_mask = BIT(0),
2204 .halt_reg = 0x4a008,
2206 .hwcg_reg = 0x4a008,
2209 .enable_reg = 0x4a008,
2210 .enable_mask = BIT(0),
2219 .halt_reg = 0x4a014,
2222 .enable_reg = 0x4a014,
2223 .enable_mask = BIT(0),
2232 .halt_reg = 0x38004,
2234 .hwcg_reg = 0x38004,
2237 .enable_reg = 0x52000,
2247 .halt_reg = 0x26010,
2249 .hwcg_reg = 0x26010,
2252 .enable_reg = 0x26010,
2253 .enable_mask = BIT(0),
2262 .halt_reg = 0x2601c,
2264 .hwcg_reg = 0x2601c,
2267 .enable_reg = 0x2601c,
2268 .enable_mask = BIT(0),
2277 .halt_reg = 0x10028,
2279 .hwcg_reg = 0x10028,
2282 .enable_reg = 0x52028,
2292 .halt_reg = 0x1002c,
2294 .hwcg_reg = 0x1002c,
2297 .enable_reg = 0x52028,
2307 .halt_reg = 0x10030,
2309 .hwcg_reg = 0x10030,
2312 .enable_reg = 0x52000,
2322 .halt_reg = 0x29288,
2324 .hwcg_reg = 0x29288,
2327 .enable_reg = 0x29288,
2328 .enable_mask = BIT(0),
2342 .halt_reg = 0x173cc,
2344 .hwcg_reg = 0x173cc,
2347 .enable_reg = 0x173cc,
2348 .enable_mask = BIT(0),
2362 .halt_reg = 0x3908c,
2364 .hwcg_reg = 0x3908c,
2367 .enable_reg = 0x3908c,
2368 .enable_mask = BIT(0),
2382 .halt_reg = 0xa108c,
2384 .hwcg_reg = 0xa108c,
2387 .enable_reg = 0xa108c,
2388 .enable_mask = BIT(0),
2402 .halt_reg = 0xa208c,
2404 .hwcg_reg = 0xa208c,
2407 .enable_reg = 0xa208c,
2408 .enable_mask = BIT(0),
2422 .halt_reg = 0x2d024,
2424 .hwcg_reg = 0x2d024,
2427 .enable_reg = 0x52028,
2437 .halt_reg = 0x2d028,
2439 .hwcg_reg = 0x2d028,
2442 .enable_reg = 0x52028,
2452 .halt_reg = 0x2d02c,
2454 .hwcg_reg = 0x2d02c,
2457 .enable_reg = 0x52018,
2467 .halt_reg = 0x2c2b4,
2470 .enable_reg = 0x52010,
2480 .halt_reg = 0x132b4,
2483 .enable_reg = 0x52010,
2493 .halt_reg = 0x10014,
2495 .hwcg_reg = 0x10014,
2498 .enable_reg = 0x52008,
2508 .halt_reg = 0x10018,
2510 .hwcg_reg = 0x10018,
2513 .enable_reg = 0x52028,
2523 .halt_reg = 0xa02b4,
2525 .hwcg_reg = 0xa02b4,
2528 .enable_reg = 0x52010,
2538 .halt_reg = 0x7115c,
2540 .hwcg_reg = 0x7115c,
2543 .enable_reg = 0x7115c,
2544 .enable_mask = BIT(0),
2553 .halt_reg = 0x2700c,
2555 .hwcg_reg = 0x2700c,
2558 .enable_reg = 0x2700c,
2559 .enable_mask = BIT(0),
2568 .halt_reg = 0x64000,
2571 .enable_reg = 0x64000,
2572 .enable_mask = BIT(0),
2586 .halt_reg = 0x65000,
2589 .enable_reg = 0x65000,
2590 .enable_mask = BIT(0),
2604 .halt_reg = 0x66000,
2607 .enable_reg = 0x66000,
2608 .enable_mask = BIT(0),
2624 .enable_reg = 0x52000,
2641 .enable_reg = 0x52000,
2656 .halt_reg = 0x71010,
2658 .hwcg_reg = 0x71010,
2661 .enable_reg = 0x71010,
2662 .enable_mask = BIT(0),
2671 .halt_reg = 0x71018,
2674 .enable_reg = 0x71018,
2675 .enable_mask = BIT(0),
2684 .halt_reg = 0xa0050,
2687 .enable_reg = 0x52010,
2702 .halt_reg = 0x2c050,
2705 .enable_reg = 0x52020,
2720 .halt_reg = 0x13050,
2723 .enable_reg = 0x52020,
2738 .halt_reg = 0xa0038,
2741 .enable_reg = 0x52010,
2756 .halt_reg = 0xa0034,
2758 .hwcg_reg = 0xa0034,
2761 .enable_reg = 0x52010,
2771 .halt_reg = 0xa0028,
2773 .hwcg_reg = 0xa0028,
2776 .enable_reg = 0x52010,
2786 .halt_reg = 0xa0044,
2789 .enable_reg = 0x52010,
2799 .halt_reg = 0xa001c,
2801 .hwcg_reg = 0xa001c,
2804 .enable_reg = 0x52010,
2814 .halt_reg = 0xa0018,
2817 .enable_reg = 0x52010,
2827 .halt_reg = 0x2c038,
2830 .enable_reg = 0x52020,
2845 .halt_reg = 0x2c034,
2847 .hwcg_reg = 0x2c034,
2850 .enable_reg = 0x52020,
2860 .halt_reg = 0x2c028,
2862 .hwcg_reg = 0x2c028,
2865 .enable_reg = 0x52020,
2875 .halt_reg = 0x2c044,
2878 .enable_reg = 0x52020,
2888 .halt_reg = 0x2c01c,
2890 .hwcg_reg = 0x2c01c,
2893 .enable_reg = 0x52020,
2903 .halt_reg = 0x2c018,
2906 .enable_reg = 0x52020,
2916 .halt_reg = 0x13038,
2919 .enable_reg = 0x52020,
2934 .halt_reg = 0x13034,
2936 .hwcg_reg = 0x13034,
2939 .enable_reg = 0x52020,
2949 .halt_reg = 0x13028,
2951 .hwcg_reg = 0x13028,
2954 .enable_reg = 0x52020,
2964 .halt_reg = 0x13044,
2967 .enable_reg = 0x52020,
2977 .halt_reg = 0x1301c,
2979 .hwcg_reg = 0x1301c,
2982 .enable_reg = 0x52020,
2992 .halt_reg = 0x13018,
2995 .enable_reg = 0x52020,
3005 .halt_reg = 0x58038,
3008 .enable_reg = 0x52020,
3023 .halt_reg = 0x58034,
3025 .hwcg_reg = 0x58034,
3028 .enable_reg = 0x52020,
3029 .enable_mask = BIT(0),
3038 .halt_reg = 0x58028,
3040 .hwcg_reg = 0x58028,
3043 .enable_reg = 0x52018,
3053 .halt_reg = 0x58044,
3056 .enable_reg = 0x52020,
3066 .halt_reg = 0x5805c,
3069 .enable_reg = 0x52020,
3084 .halt_reg = 0x58050,
3087 .enable_reg = 0x52020,
3097 .halt_reg = 0x58060,
3100 .enable_reg = 0x52020,
3115 .halt_reg = 0x5801c,
3117 .hwcg_reg = 0x5801c,
3120 .enable_reg = 0x52018,
3130 .halt_reg = 0x58018,
3133 .enable_reg = 0x52018,
3143 .halt_reg = 0x6b038,
3146 .enable_reg = 0x52008,
3161 .halt_reg = 0x6b034,
3163 .hwcg_reg = 0x6b034,
3166 .enable_reg = 0x52008,
3176 .halt_reg = 0x6b028,
3178 .hwcg_reg = 0x6b028,
3181 .enable_reg = 0x52008,
3191 .halt_reg = 0x6b050,
3194 .enable_reg = 0x52000,
3209 .halt_reg = 0x6b044,
3212 .enable_reg = 0x52008,
3222 .halt_reg = 0x6b054,
3225 .enable_reg = 0x52010,
3240 .halt_reg = 0x6b01c,
3242 .hwcg_reg = 0x6b01c,
3245 .enable_reg = 0x52008,
3246 .enable_mask = BIT(0),
3255 .halt_reg = 0x6b018,
3258 .enable_reg = 0x52008,
3268 .halt_reg = 0x2f038,
3271 .enable_reg = 0x52018,
3286 .halt_reg = 0x2f034,
3288 .hwcg_reg = 0x2f034,
3291 .enable_reg = 0x52018,
3301 .halt_reg = 0x2f028,
3303 .hwcg_reg = 0x2f028,
3306 .enable_reg = 0x52018,
3316 .halt_reg = 0x2f050,
3319 .enable_reg = 0x52018,
3334 .halt_reg = 0x2f044,
3337 .enable_reg = 0x52018,
3347 .halt_reg = 0x2f054,
3350 .enable_reg = 0x52018,
3365 .halt_reg = 0x2f01c,
3367 .hwcg_reg = 0x2f01c,
3370 .enable_reg = 0x52018,
3380 .halt_reg = 0x2f018,
3383 .enable_reg = 0x52018,
3393 .halt_reg = 0x31038,
3396 .enable_reg = 0x52018,
3411 .halt_reg = 0x31034,
3413 .hwcg_reg = 0x31034,
3416 .enable_reg = 0x52018,
3426 .halt_reg = 0x31028,
3428 .hwcg_reg = 0x31028,
3431 .enable_reg = 0x52018,
3441 .halt_reg = 0x31044,
3444 .enable_reg = 0x52018,
3454 .halt_reg = 0x3105c,
3457 .enable_reg = 0x52018,
3472 .halt_reg = 0x31050,
3475 .enable_reg = 0x52018,
3485 .halt_reg = 0x31060,
3488 .enable_reg = 0x52018,
3503 .halt_reg = 0x3101c,
3505 .hwcg_reg = 0x3101c,
3508 .enable_reg = 0x52018,
3518 .halt_reg = 0x31018,
3521 .enable_reg = 0x52018,
3531 .halt_reg = 0x8d038,
3534 .enable_reg = 0x52000,
3549 .halt_reg = 0x8d034,
3551 .hwcg_reg = 0x8d034,
3554 .enable_reg = 0x52000,
3564 .halt_reg = 0x8d028,
3566 .hwcg_reg = 0x8d028,
3569 .enable_reg = 0x52000,
3579 .halt_reg = 0x8d044,
3582 .enable_reg = 0x52000,
3592 .halt_reg = 0x8d05c,
3595 .enable_reg = 0x52000,
3610 .halt_reg = 0x8d050,
3613 .enable_reg = 0x52000,
3623 .halt_reg = 0x8d060,
3626 .enable_reg = 0x52010,
3641 .halt_reg = 0x8d01c,
3643 .hwcg_reg = 0x8d01c,
3646 .enable_reg = 0x52000,
3656 .halt_reg = 0x8d018,
3659 .enable_reg = 0x52000,
3669 .halt_reg = 0xa4008,
3671 .hwcg_reg = 0xa4008,
3674 .enable_reg = 0x52028,
3684 .halt_reg = 0xa4004,
3687 .enable_reg = 0x52028,
3702 .halt_reg = 0x3300c,
3705 .enable_reg = 0x3300c,
3706 .enable_mask = BIT(0),
3720 .halt_reg = 0x33004,
3722 .hwcg_reg = 0x33004,
3725 .enable_reg = 0x33004,
3726 .enable_mask = BIT(0),
3735 .halt_reg = 0x33008,
3738 .enable_reg = 0x33008,
3739 .enable_mask = BIT(0),
3748 .halt_reg = 0x4a018,
3750 .hwcg_reg = 0x4a018,
3753 .enable_reg = 0x4a018,
3754 .enable_mask = BIT(0),
3763 .halt_reg = 0x26008,
3765 .hwcg_reg = 0x26008,
3768 .enable_reg = 0x26008,
3769 .enable_mask = BIT(0),
3778 .halt_reg = 0x2600c,
3780 .hwcg_reg = 0x2600c,
3783 .enable_reg = 0x2600c,
3784 .enable_mask = BIT(0),
3793 .halt_reg = 0x27008,
3795 .hwcg_reg = 0x27008,
3798 .enable_reg = 0x27008,
3799 .enable_mask = BIT(0),
3808 .halt_reg = 0x71008,
3810 .hwcg_reg = 0x71008,
3813 .enable_reg = 0x71008,
3814 .enable_mask = BIT(0),
3823 .halt_reg = 0x32014,
3825 .hwcg_reg = 0x32014,
3828 .enable_reg = 0x32014,
3829 .enable_mask = BIT(0),
3838 .halt_reg = 0x32008,
3840 .hwcg_reg = 0x32008,
3843 .enable_reg = 0x32008,
3844 .enable_mask = BIT(0),
3853 .halt_reg = 0x32010,
3855 .hwcg_reg = 0x32010,
3858 .enable_reg = 0x32010,
3859 .enable_mask = BIT(0),
3868 .halt_reg = 0x3200c,
3870 .hwcg_reg = 0x3200c,
3873 .enable_reg = 0x3200c,
3874 .enable_mask = BIT(0),
3883 .halt_reg = 0x23018,
3886 .enable_reg = 0x52020,
3896 .halt_reg = 0x23008,
3899 .enable_reg = 0x52020,
3909 .halt_reg = 0x42280,
3912 .enable_reg = 0x52028,
3927 .halt_reg = 0x423c0,
3930 .enable_reg = 0x52028,
3945 .halt_reg = 0x42004,
3948 .enable_reg = 0x52020,
3963 .halt_reg = 0x4213c,
3966 .enable_reg = 0x52020,
3981 .halt_reg = 0x42274,
3984 .enable_reg = 0x52020,
3999 .halt_reg = 0x423b4,
4002 .enable_reg = 0x52020,
4017 .halt_reg = 0x424f4,
4020 .enable_reg = 0x52020,
4035 .halt_reg = 0x4262c,
4038 .enable_reg = 0x52020,
4053 .halt_reg = 0x42764,
4056 .enable_reg = 0x52020,
4071 .halt_reg = 0x4289c,
4074 .enable_reg = 0x52020,
4089 .halt_reg = 0x23168,
4092 .enable_reg = 0x52008,
4102 .halt_reg = 0x23158,
4105 .enable_reg = 0x52008,
4115 .halt_reg = 0x18280,
4118 .enable_reg = 0x52028,
4133 .halt_reg = 0x183c0,
4136 .enable_reg = 0x52028,
4151 .halt_reg = 0x18004,
4154 .enable_reg = 0x52008,
4169 .halt_reg = 0x1813c,
4172 .enable_reg = 0x52008,
4187 .halt_reg = 0x18274,
4190 .enable_reg = 0x52008,
4205 .halt_reg = 0x183b4,
4208 .enable_reg = 0x52008,
4223 .halt_reg = 0x184f4,
4226 .enable_reg = 0x52008,
4241 .halt_reg = 0x1862c,
4244 .enable_reg = 0x52008,
4259 .halt_reg = 0x18764,
4262 .enable_reg = 0x52008,
4277 .halt_reg = 0x1889c,
4280 .enable_reg = 0x52010,
4295 .halt_reg = 0x232b8,
4298 .enable_reg = 0x52010,
4308 .halt_reg = 0x232a8,
4311 .enable_reg = 0x52010,
4312 .enable_mask = BIT(0),
4321 .halt_reg = 0x1e280,
4324 .enable_reg = 0x52028,
4339 .halt_reg = 0x1e3c0,
4342 .enable_reg = 0x52028,
4357 .halt_reg = 0x1e004,
4360 .enable_reg = 0x52010,
4375 .halt_reg = 0x1e13c,
4378 .enable_reg = 0x52010,
4393 .halt_reg = 0x1e274,
4396 .enable_reg = 0x52010,
4411 .halt_reg = 0x1e3b4,
4414 .enable_reg = 0x52010,
4429 .halt_reg = 0x1e4f4,
4432 .enable_reg = 0x52010,
4447 .halt_reg = 0x1e62c,
4450 .enable_reg = 0x52010,
4465 .halt_reg = 0x1e764,
4468 .enable_reg = 0x52010,
4483 .halt_reg = 0x1e89c,
4486 .enable_reg = 0x52010,
4501 .halt_reg = 0x23000,
4503 .hwcg_reg = 0x23000,
4506 .enable_reg = 0x52020,
4516 .halt_reg = 0x23004,
4518 .hwcg_reg = 0x23004,
4521 .enable_reg = 0x52020,
4531 .halt_reg = 0x23150,
4533 .hwcg_reg = 0x23150,
4536 .enable_reg = 0x52008,
4546 .halt_reg = 0x23154,
4548 .hwcg_reg = 0x23154,
4551 .enable_reg = 0x52008,
4561 .halt_reg = 0x232a0,
4563 .hwcg_reg = 0x232a0,
4566 .enable_reg = 0x52010,
4576 .halt_reg = 0x232a4,
4578 .hwcg_reg = 0x232a4,
4581 .enable_reg = 0x52010,
4591 .halt_reg = 0x14010,
4594 .enable_reg = 0x14010,
4595 .enable_mask = BIT(0),
4604 .halt_reg = 0x14004,
4607 .enable_reg = 0x14004,
4608 .enable_mask = BIT(0),
4622 .halt_reg = 0x16010,
4625 .enable_reg = 0x16010,
4626 .enable_mask = BIT(0),
4635 .halt_reg = 0x16004,
4638 .enable_reg = 0x16004,
4639 .enable_mask = BIT(0),
4653 .halt_reg = 0x2d014,
4655 .hwcg_reg = 0x2d014,
4658 .enable_reg = 0x2d014,
4659 .enable_mask = BIT(0),
4668 .halt_reg = 0x77024,
4670 .hwcg_reg = 0x77024,
4673 .enable_reg = 0x77024,
4674 .enable_mask = BIT(0),
4683 .halt_reg = 0x77018,
4685 .hwcg_reg = 0x77018,
4688 .enable_reg = 0x77018,
4689 .enable_mask = BIT(0),
4703 .halt_reg = 0x77074,
4705 .hwcg_reg = 0x77074,
4708 .enable_reg = 0x77074,
4709 .enable_mask = BIT(0),
4723 .halt_reg = 0x770b0,
4725 .hwcg_reg = 0x770b0,
4728 .enable_reg = 0x770b0,
4729 .enable_mask = BIT(0),
4743 .halt_reg = 0x7702c,
4746 .enable_reg = 0x7702c,
4747 .enable_mask = BIT(0),
4756 .halt_reg = 0x770cc,
4759 .enable_reg = 0x770cc,
4760 .enable_mask = BIT(0),
4769 .halt_reg = 0x77028,
4772 .enable_reg = 0x77028,
4773 .enable_mask = BIT(0),
4782 .halt_reg = 0x77068,
4784 .hwcg_reg = 0x77068,
4787 .enable_reg = 0x77068,
4788 .enable_mask = BIT(0),
4802 .halt_reg = 0x29018,
4805 .enable_reg = 0x29018,
4806 .enable_mask = BIT(0),
4820 .halt_reg = 0x29028,
4823 .enable_reg = 0x29028,
4824 .enable_mask = BIT(0),
4838 .halt_reg = 0x29024,
4841 .enable_reg = 0x29024,
4842 .enable_mask = BIT(0),
4851 .halt_reg = 0x17018,
4854 .enable_reg = 0x17018,
4855 .enable_mask = BIT(0),
4869 .halt_reg = 0x17028,
4872 .enable_reg = 0x17028,
4873 .enable_mask = BIT(0),
4887 .halt_reg = 0x17024,
4890 .enable_reg = 0x17024,
4891 .enable_mask = BIT(0),
4900 .halt_reg = 0x39018,
4903 .enable_reg = 0x39018,
4904 .enable_mask = BIT(0),
4918 .halt_reg = 0x39028,
4921 .enable_reg = 0x39028,
4922 .enable_mask = BIT(0),
4936 .halt_reg = 0x39024,
4939 .enable_reg = 0x39024,
4940 .enable_mask = BIT(0),
4949 .halt_reg = 0xa1018,
4952 .enable_reg = 0xa1018,
4953 .enable_mask = BIT(0),
4967 .halt_reg = 0xa1028,
4970 .enable_reg = 0xa1028,
4971 .enable_mask = BIT(0),
4985 .halt_reg = 0xa1024,
4988 .enable_reg = 0xa1024,
4989 .enable_mask = BIT(0),
4998 .halt_reg = 0xa2018,
5001 .enable_reg = 0xa2018,
5002 .enable_mask = BIT(0),
5016 .halt_reg = 0xa2028,
5019 .enable_reg = 0xa2028,
5020 .enable_mask = BIT(0),
5034 .halt_reg = 0xa2024,
5037 .enable_reg = 0xa2024,
5038 .enable_mask = BIT(0),
5047 .halt_reg = 0x17288,
5050 .enable_reg = 0x17288,
5051 .enable_mask = BIT(0),
5065 .halt_reg = 0x1728c,
5068 .enable_reg = 0x1728c,
5069 .enable_mask = BIT(0),
5083 .halt_reg = 0x17290,
5086 .enable_reg = 0x17290,
5087 .enable_mask = BIT(0),
5096 .halt_reg = 0x17298,
5099 .enable_reg = 0x17298,
5100 .enable_mask = BIT(0),
5109 .halt_reg = 0x39060,
5112 .enable_reg = 0x39060,
5113 .enable_mask = BIT(0),
5127 .halt_reg = 0x39064,
5130 .enable_reg = 0x39064,
5131 .enable_mask = BIT(0),
5145 .reg = 0x3906c,
5146 .shift = 0,
5160 .halt_reg = 0x39068,
5162 .hwcg_reg = 0x39068,
5165 .enable_reg = 0x39068,
5166 .enable_mask = BIT(0),
5180 .halt_reg = 0xa1060,
5183 .enable_reg = 0xa1060,
5184 .enable_mask = BIT(0),
5198 .halt_reg = 0xa1064,
5201 .enable_reg = 0xa1064,
5202 .enable_mask = BIT(0),
5216 .reg = 0xa106c,
5217 .shift = 0,
5231 .halt_reg = 0xa1068,
5233 .hwcg_reg = 0xa1068,
5236 .enable_reg = 0xa1068,
5237 .enable_mask = BIT(0),
5251 .halt_reg = 0xa2060,
5254 .enable_reg = 0xa2060,
5255 .enable_mask = BIT(0),
5269 .halt_reg = 0xa2064,
5272 .enable_reg = 0xa2064,
5273 .enable_mask = BIT(0),
5287 .reg = 0xa206c,
5288 .shift = 0,
5302 .halt_reg = 0xa2068,
5304 .hwcg_reg = 0xa2068,
5307 .enable_reg = 0xa2068,
5308 .enable_mask = BIT(0),
5322 .halt_reg = 0x9f0a8,
5324 .hwcg_reg = 0x9f0a8,
5327 .enable_reg = 0x9f0a8,
5328 .enable_mask = BIT(0),
5337 .halt_reg = 0x9f060,
5340 .enable_reg = 0x9f060,
5341 .enable_mask = BIT(0),
5350 .halt_reg = 0x9f108,
5353 .enable_reg = 0x9f108,
5354 .enable_mask = BIT(0),
5363 .halt_reg = 0x9f018,
5366 .enable_reg = 0x9f018,
5367 .enable_mask = BIT(0),
5381 .halt_reg = 0x9f0d8,
5384 .enable_reg = 0x9f0d8,
5385 .enable_mask = BIT(0),
5394 .halt_reg = 0x9f048,
5397 .enable_reg = 0x52010,
5407 .halt_reg = 0x9f0b0,
5410 .enable_reg = 0x9f0b0,
5411 .enable_mask = BIT(0),
5420 .halt_reg = 0x9f0c0,
5423 .enable_reg = 0x9f0c0,
5424 .enable_mask = BIT(0),
5433 .halt_reg = 0x9f0a4,
5435 .hwcg_reg = 0x9f0a4,
5438 .enable_reg = 0x9f0a4,
5439 .enable_mask = BIT(0),
5448 .halt_reg = 0x9f044,
5451 .enable_reg = 0x9f044,
5452 .enable_mask = BIT(0),
5466 .halt_reg = 0x9f054,
5469 .enable_reg = 0x9f054,
5470 .enable_mask = BIT(0),
5479 .halt_reg = 0x9f088,
5481 .hwcg_reg = 0x9f088,
5484 .enable_reg = 0x9f088,
5485 .enable_mask = BIT(0),
5499 .halt_reg = 0x2b0a8,
5501 .hwcg_reg = 0x2b0a8,
5504 .enable_reg = 0x2b0a8,
5505 .enable_mask = BIT(0),
5514 .halt_reg = 0x2b060,
5517 .enable_reg = 0x2b060,
5518 .enable_mask = BIT(0),
5527 .halt_reg = 0x2b108,
5530 .enable_reg = 0x2b108,
5531 .enable_mask = BIT(0),
5540 .halt_reg = 0x2b018,
5543 .enable_reg = 0x2b018,
5544 .enable_mask = BIT(0),
5558 .halt_reg = 0x2b0d8,
5561 .enable_reg = 0x2b0d8,
5562 .enable_mask = BIT(0),
5571 .halt_reg = 0x2b048,
5574 .enable_reg = 0x52028,
5575 .enable_mask = BIT(0),
5584 .halt_reg = 0x2b0b0,
5587 .enable_reg = 0x2b0b0,
5588 .enable_mask = BIT(0),
5597 .halt_reg = 0x2b0c0,
5600 .enable_reg = 0x2b0c0,
5601 .enable_mask = BIT(0),
5610 .halt_reg = 0x2b0a4,
5612 .hwcg_reg = 0x2b0a4,
5615 .enable_reg = 0x2b0a4,
5616 .enable_mask = BIT(0),
5625 .halt_reg = 0x2b044,
5628 .enable_reg = 0x2b044,
5629 .enable_mask = BIT(0),
5643 .halt_reg = 0x2b054,
5646 .enable_reg = 0x2b054,
5647 .enable_mask = BIT(0),
5656 .halt_reg = 0x2b088,
5658 .hwcg_reg = 0x2b088,
5661 .enable_reg = 0x2b088,
5662 .enable_mask = BIT(0),
5676 .halt_reg = 0x110a8,
5678 .hwcg_reg = 0x110a8,
5681 .enable_reg = 0x110a8,
5682 .enable_mask = BIT(0),
5691 .halt_reg = 0x11060,
5694 .enable_reg = 0x11060,
5695 .enable_mask = BIT(0),
5704 .halt_reg = 0x11108,
5707 .enable_reg = 0x11108,
5708 .enable_mask = BIT(0),
5717 .halt_reg = 0x11018,
5720 .enable_reg = 0x11018,
5721 .enable_mask = BIT(0),
5735 .halt_reg = 0x110d8,
5738 .enable_reg = 0x110d8,
5739 .enable_mask = BIT(0),
5748 .halt_reg = 0x11048,
5751 .enable_reg = 0x52028,
5761 .halt_reg = 0x110b0,
5764 .enable_reg = 0x110b0,
5765 .enable_mask = BIT(0),
5774 .halt_reg = 0x110c0,
5777 .enable_reg = 0x110c0,
5778 .enable_mask = BIT(0),
5787 .halt_reg = 0x110a4,
5789 .hwcg_reg = 0x110a4,
5792 .enable_reg = 0x110a4,
5793 .enable_mask = BIT(0),
5802 .halt_reg = 0x11044,
5805 .enable_reg = 0x11044,
5806 .enable_mask = BIT(0),
5820 .halt_reg = 0x11054,
5823 .enable_reg = 0x11054,
5824 .enable_mask = BIT(0),
5833 .halt_reg = 0x11088,
5835 .hwcg_reg = 0x11088,
5838 .enable_reg = 0x11088,
5839 .enable_mask = BIT(0),
5853 .halt_reg = 0x32018,
5855 .hwcg_reg = 0x32018,
5858 .enable_reg = 0x32018,
5859 .enable_mask = BIT(0),
5868 .halt_reg = 0x32024,
5870 .hwcg_reg = 0x32024,
5873 .enable_reg = 0x32024,
5874 .enable_mask = BIT(0),
5883 .gdscr = 0xa0004,
5884 .en_rest_wait_val = 0x2,
5885 .en_few_wait_val = 0x2,
5886 .clk_dis_wait_val = 0xf,
5895 .gdscr = 0x2c004,
5896 .en_rest_wait_val = 0x2,
5897 .en_few_wait_val = 0x2,
5898 .clk_dis_wait_val = 0xf,
5907 .gdscr = 0x13004,
5908 .en_rest_wait_val = 0x2,
5909 .en_few_wait_val = 0x2,
5910 .clk_dis_wait_val = 0xf,
5919 .gdscr = 0x58004,
5920 .en_rest_wait_val = 0x2,
5921 .en_few_wait_val = 0x2,
5922 .clk_dis_wait_val = 0xf,
5931 .gdscr = 0x3e000,
5932 .en_rest_wait_val = 0x2,
5933 .en_few_wait_val = 0x2,
5934 .clk_dis_wait_val = 0x2,
5943 .gdscr = 0x6b004,
5944 .en_rest_wait_val = 0x2,
5945 .en_few_wait_val = 0x2,
5946 .clk_dis_wait_val = 0xf,
5955 .gdscr = 0x6c000,
5956 .en_rest_wait_val = 0x2,
5957 .en_few_wait_val = 0x2,
5958 .clk_dis_wait_val = 0x2,
5967 .gdscr = 0x2f004,
5968 .en_rest_wait_val = 0x2,
5969 .en_few_wait_val = 0x2,
5970 .clk_dis_wait_val = 0xf,
5979 .gdscr = 0x30000,
5980 .en_rest_wait_val = 0x2,
5981 .en_few_wait_val = 0x2,
5982 .clk_dis_wait_val = 0x2,
5991 .gdscr = 0x8e000,
5992 .en_rest_wait_val = 0x2,
5993 .en_few_wait_val = 0x2,
5994 .clk_dis_wait_val = 0x2,
6003 .gdscr = 0x31004,
6004 .en_rest_wait_val = 0x2,
6005 .en_few_wait_val = 0x2,
6006 .clk_dis_wait_val = 0xf,
6015 .gdscr = 0x8d004,
6016 .en_rest_wait_val = 0x2,
6017 .en_few_wait_val = 0x2,
6018 .clk_dis_wait_val = 0xf,
6027 .gdscr = 0x9e000,
6028 .en_rest_wait_val = 0x2,
6029 .en_few_wait_val = 0x2,
6030 .clk_dis_wait_val = 0x2,
6039 .gdscr = 0x77004,
6040 .en_rest_wait_val = 0x2,
6041 .en_few_wait_val = 0x2,
6042 .clk_dis_wait_val = 0xf,
6051 .gdscr = 0x29004,
6052 .en_rest_wait_val = 0x2,
6053 .en_few_wait_val = 0x2,
6054 .clk_dis_wait_val = 0xf,
6063 .gdscr = 0x17004,
6064 .en_rest_wait_val = 0x2,
6065 .en_few_wait_val = 0x2,
6066 .clk_dis_wait_val = 0xf,
6075 .gdscr = 0x39004,
6076 .en_rest_wait_val = 0x2,
6077 .en_few_wait_val = 0x2,
6078 .clk_dis_wait_val = 0xf,
6087 .gdscr = 0xa1004,
6088 .en_rest_wait_val = 0x2,
6089 .en_few_wait_val = 0x2,
6090 .clk_dis_wait_val = 0xf,
6099 .gdscr = 0xa2004,
6100 .en_rest_wait_val = 0x2,
6101 .en_few_wait_val = 0x2,
6102 .clk_dis_wait_val = 0xf,
6111 .gdscr = 0x1900c,
6112 .en_rest_wait_val = 0x2,
6113 .en_few_wait_val = 0x2,
6114 .clk_dis_wait_val = 0x2,
6123 .gdscr = 0x5400c,
6124 .en_rest_wait_val = 0x2,
6125 .en_few_wait_val = 0x2,
6126 .clk_dis_wait_val = 0x2,
6135 .gdscr = 0x9f004,
6136 .en_rest_wait_val = 0x2,
6137 .en_few_wait_val = 0x2,
6138 .clk_dis_wait_val = 0xf,
6147 .gdscr = 0x2b004,
6148 .en_rest_wait_val = 0x2,
6149 .en_few_wait_val = 0x2,
6150 .clk_dis_wait_val = 0xf,
6159 .gdscr = 0x11004,
6160 .en_rest_wait_val = 0x2,
6161 .en_few_wait_val = 0x2,
6162 .clk_dis_wait_val = 0xf,
6171 .gdscr = 0x50024,
6172 .en_rest_wait_val = 0x2,
6173 .en_few_wait_val = 0x2,
6174 .clk_dis_wait_val = 0x2,
6183 .gdscr = 0x2a024,
6184 .en_rest_wait_val = 0x2,
6185 .en_few_wait_val = 0x2,
6186 .clk_dis_wait_val = 0x2,
6195 .gdscr = 0xa3024,
6196 .en_rest_wait_val = 0x2,
6197 .en_few_wait_val = 0x2,
6198 .clk_dis_wait_val = 0x2,
6589 [GCC_AV1E_BCR] = { 0x4a000 },
6590 [GCC_CAMERA_BCR] = { 0x26000 },
6591 [GCC_DISPLAY_BCR] = { 0x27000 },
6592 [GCC_GPU_BCR] = { 0x71000 },
6593 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
6594 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
6595 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
6596 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
6597 [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },
6598 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
6599 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
6600 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
6601 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
6602 [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },
6603 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },
6604 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },
6605 [GCC_PCIE_2_PHY_BCR] = { 0xa501c },
6606 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },
6607 [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },
6608 [GCC_PCIE_3_BCR] = { 0x58000 },
6609 [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },
6610 [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },
6611 [GCC_PCIE_3_PHY_BCR] = { 0xab01c },
6612 [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },
6613 [GCC_PCIE_4_BCR] = { 0x6b000 },
6614 [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },
6615 [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },
6616 [GCC_PCIE_4_PHY_BCR] = { 0xb301c },
6617 [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },
6618 [GCC_PCIE_5_BCR] = { 0x2f000 },
6619 [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },
6620 [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },
6621 [GCC_PCIE_5_PHY_BCR] = { 0xaa01c },
6622 [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },
6623 [GCC_PCIE_6A_BCR] = { 0x31000 },
6624 [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },
6625 [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },
6626 [GCC_PCIE_6A_PHY_BCR] = { 0xac01c },
6627 [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },
6628 [GCC_PCIE_6B_BCR] = { 0x8d000 },
6629 [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },
6630 [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },
6631 [GCC_PCIE_6B_PHY_BCR] = { 0xb501c },
6632 [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },
6633 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
6634 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
6635 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
6636 [GCC_PCIE_RSCC_BCR] = { 0xa4000 },
6637 [GCC_PDM_BCR] = { 0x33000 },
6638 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },
6639 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
6640 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
6641 [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },
6642 [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },
6643 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
6644 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
6645 [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },
6646 [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },
6647 [GCC_SDCC2_BCR] = { 0x14000 },
6648 [GCC_SDCC4_BCR] = { 0x16000 },
6649 [GCC_UFS_PHY_BCR] = { 0x77000 },
6650 [GCC_USB20_PRIM_BCR] = { 0x29000 },
6651 [GCC_USB30_MP_BCR] = { 0x17000 },
6652 [GCC_USB30_PRIM_BCR] = { 0x39000 },
6653 [GCC_USB30_SEC_BCR] = { 0xa1000 },
6654 [GCC_USB30_TERT_BCR] = { 0xa2000 },
6655 [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },
6656 [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },
6657 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
6658 [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },
6659 [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },
6660 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
6661 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
6662 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
6663 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
6664 [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
6665 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
6666 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
6667 [GCC_USB4_0_BCR] = { 0x9f000 },
6668 [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
6669 [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
6670 [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
6671 [GCC_USB4_1_BCR] = { 0x2b000 },
6672 [GCC_USB4_2_BCR] = { 0x11000 },
6673 [GCC_USB_0_PHY_BCR] = { 0x50020 },
6674 [GCC_USB_1_PHY_BCR] = { 0x2a020 },
6675 [GCC_USB_2_PHY_BCR] = { 0xa3020 },
6676 [GCC_VIDEO_BCR] = { 0x32000 },
6710 .max_register = 0x1f41f0,
6745 qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ in gcc_x1e80100_probe()
6746 qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ in gcc_x1e80100_probe()
6747 qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ in gcc_x1e80100_probe()
6748 qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ in gcc_x1e80100_probe()
6749 qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ in gcc_x1e80100_probe()
6750 qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ in gcc_x1e80100_probe()
6751 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_x1e80100_probe()
6754 regmap_write(regmap, 0x52224, 0x0); in gcc_x1e80100_probe()