88 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
114 /* Extract divider instance from clock hardware instance */
148  * struct clk_wzrd_divider - clock divider specific to clk_wzrd
151  * @base:	base address of register containing the divider
152  * @offset:	offset address of register containing the divider
153  * @shift:	shift to the divider bit field
154  * @width:	width of the divider bit field
155  * @flags:	clk_wzrd divider flags
156  * @table:	array of value/divider pairs, last entry should have div = 0
159  * @d:	value of the common divider
160  * @o:	value of the leaf divider
161  * @o_frac:	value of the fractional leaf divider
177 	spinlock_t *lock;  /* divider lock */
199 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_ver()  local
200 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_rate_ver()
224 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate()  local
225 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_rate()
228 	val = readl(div_addr) >> divider->shift;  in clk_wzrd_recalc_rate()
229 	val &= div_mask(divider->width);  in clk_wzrd_recalc_rate()
231 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_wzrd_recalc_rate()
232 			divider->flags, divider->width);  in clk_wzrd_recalc_rate()
238 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_ver_dynamic_reconfig()  local
239 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_ver_dynamic_reconfig()
244 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_ver_dynamic_reconfig()
264 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_ver_dynamic_reconfig()
272 	       divider->base + WZRD_DR_INIT_VERSAL_OFFSET);  in clk_wzrd_ver_dynamic_reconfig()
275 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_ver_dynamic_reconfig()
279 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_ver_dynamic_reconfig()
286 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig()  local
287 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig()
292 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
304 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
312 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
314 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
317 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
321 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
342 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_get_divisors_ver()  local
365 						divider->m = m;  in clk_wzrd_get_divisors_ver()
366 						divider->d = d;  in clk_wzrd_get_divisors_ver()
367 						divider->o = o;  in clk_wzrd_get_divisors_ver()
380 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_get_divisors()  local
406 				divider->m = m >> 3;  in clk_wzrd_get_divisors()
407 				divider->m_frac = (m - (divider->m << 3)) * 125;  in clk_wzrd_get_divisors()
408 				divider->d = d;  in clk_wzrd_get_divisors()
409 				divider->o = o >> 3;  in clk_wzrd_get_divisors()
410 				divider->o_frac = (o - (divider->o << 3)) * 125;  in clk_wzrd_get_divisors()
417 static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)  in clk_wzrd_reconfig()  argument
423 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_reconfig()
432 	return readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_reconfig()
441 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_ver_all_nolock()  local
449 	writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));  in clk_wzrd_dynamic_ver_all_nolock()
451 	m = divider->m;  in clk_wzrd_dynamic_ver_all_nolock()
454 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
462 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
465 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
468 	value2 = divider->d;  in clk_wzrd_dynamic_ver_all_nolock()
472 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
475 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));  in clk_wzrd_dynamic_ver_all_nolock()
477 	value = divider->o;  in clk_wzrd_dynamic_ver_all_nolock()
479 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
493 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
496 	writel(regval, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
498 	div_addr = divider->base + WZRD_DR_INIT_VERSAL_OFFSET;  in clk_wzrd_dynamic_ver_all_nolock()
500 	return clk_wzrd_reconfig(divider, div_addr);  in clk_wzrd_dynamic_ver_all_nolock()
506 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all_nolock()  local
515 	reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, divider->o) |  in clk_wzrd_dynamic_all_nolock()
516 	      FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, divider->o_frac);  in clk_wzrd_dynamic_all_nolock()
518 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));  in clk_wzrd_dynamic_all_nolock()
519 	reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |  in clk_wzrd_dynamic_all_nolock()
520 	      FIELD_PREP(WZRD_CLKFBOUT_MULT_FRAC_MASK, divider->m_frac) |  in clk_wzrd_dynamic_all_nolock()
521 	      FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);  in clk_wzrd_dynamic_all_nolock()
522 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));  in clk_wzrd_dynamic_all_nolock()
523 	writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));  in clk_wzrd_dynamic_all_nolock()
524 	div_addr = divider->base + WZRD_DR_INIT_REG_OFFSET;  in clk_wzrd_dynamic_all_nolock()
525 	return clk_wzrd_reconfig(divider, div_addr);  in clk_wzrd_dynamic_all_nolock()
531 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all()  local
535 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_all()
539 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_all()
547 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all_ver()  local
551 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_all_ver()
555 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_all_ver()
563 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_all()  local
567 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 0));  in clk_wzrd_recalc_rate_all()
571 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 2));  in clk_wzrd_recalc_rate_all()
582 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_all_ver()  local
586 	edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &  in clk_wzrd_recalc_rate_all_ver()
589 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));  in clk_wzrd_recalc_rate_all_ver()
597 	regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &  in clk_wzrd_recalc_rate_all_ver()
600 		regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))  in clk_wzrd_recalc_rate_all_ver()
609 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));  in clk_wzrd_recalc_rate_all_ver()
614 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));  in clk_wzrd_recalc_rate_all_ver()
629 	edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &  in clk_wzrd_recalc_rate_all_ver()
631 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));  in clk_wzrd_recalc_rate_all_ver()
641 	return divider_recalc_rate(hw, parent_rate, div, divider->table,  in clk_wzrd_recalc_rate_all_ver()
642 			divider->flags, divider->width);  in clk_wzrd_recalc_rate_all_ver()
648 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_round_rate_all()  local
656 	m = divider->m;  in clk_wzrd_round_rate_all()
657 	d = divider->d;  in clk_wzrd_round_rate_all()
658 	o = divider->o;  in clk_wzrd_round_rate_all()
660 	rate = div_u64(*prate * (m * 1000 + divider->m_frac), d * (o * 1000 + divider->o_frac));  in clk_wzrd_round_rate_all()
667 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_ver_round_rate_all()  local
676 	m = divider->m;  in clk_wzrd_ver_round_rate_all()
677 	d = divider->d;  in clk_wzrd_ver_round_rate_all()
678 	o = divider->o;  in clk_wzrd_ver_round_rate_all()
681 	int_freq =  divider_recalc_rate(hw, *prate * m, div, divider->table,  in clk_wzrd_ver_round_rate_all()
682 					divider->flags, divider->width);  in clk_wzrd_ver_round_rate_all()
720 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_ratef()  local
721 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_ratef()
724 	div = val & div_mask(divider->width);  in clk_wzrd_recalc_ratef()
736 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig_f()  local
737 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig_f()
754 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
762 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
764 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
767 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
1096 		dev_err(dev, "unable to register divider clock\n");  in clk_wzrd_register_output_clocks()
1136 			dev_err(dev, "unable to register divider clock\n");  in clk_wzrd_register_output_clocks()