Lines Matching full:rank

110 #define I3000_C0DRB	0x100	/* Channel 0 DRAM Rank Boundary (8b x 4)
112 				 * 7:0   Channel 0 DRAM Rank Boundary Address
114 #define I3000_C1DRB	0x180	/* Channel 1 DRAM Rank Boundary (8b x 4)
116 				 * 7:0   Channel 1 DRAM Rank Boundary Address
119 #define I3000_C0DRA	0x108	/* Channel 0 DRAM Rank Attribute (8b x 2)
122 				 * 6:4   DRAM odd Rank Attribute
124 				 * 2:0   DRAM even Rank Attribute
127 				 * size of the corresponding rank:
135 #define I3000_C1DRA	0x188	/* Channel 1 DRAM Rank Attribute (8b x 2) */
298 	 * If the rank boundaries for the two channels are different  in i3000_is_interleaved()
381 	 * The dram rank boundary (DRB) reg values are boundary addresses  in i3000_probe1()
382 	 * for each DRAM rank with a granularity of 32MB.  DRB regs are  in i3000_probe1()