Lines Matching full:configuration
240 * configuration of the device
793 * @valid_params: Bitfield defining validity of ring configuration parameters.
794 * The ring configuration fields are not valid, and will not be used for
795 * ring configuration, if their corresponding valid bit is zero.
896 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
901 * @flow_index: UDMAP receive flow index for non-optional configuration.
905 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
961 * flow optional configuration
965 * @flow_index: UDMAP receive flow index for optional configuration.
997 * in the TISCI header via the RM board configuration resource assignment
1002 * @valid_params: Bitfield defining validity of tx channel configuration
1003 * parameters. The tx channel configuration fields are not valid, and will not
1004 * be used for ch configuration, if their corresponding valid bit is zero.
1028 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
1033 * configuration to be programmed into the tx_filt_einfo field of the
1037 * configuration to be programmed into the tx_filt_pswords field of the
1041 * interpretation configuration to be programmed into the tx_atype field of
1045 * passing mechanism configuration to be programmed into the tx_chan_type
1049 * configuration to be programmed into the tx_supr_tdpkt field of the channel's
1053 * fetch configuration to be programmed into the tx_fetch_size field of the
1058 * configuration to be programmed into the count field of the TCHAN_TCREDIT
1061 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
1064 * requesting configuration of the transmit channel.
1075 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
1081 * configuration to be programmed into the priority field of the channel's
1084 * @tx_burst_size: UDMAP transmit channel burst size configuration to be
1087 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
1125 * in the TISCI header via the RM board configuration resource assignment
1130 * @valid_params: Bitfield defining validity of rx channel configuration
1132 * The rx channel configuration fields are not valid, and will not be used for
1133 * ch configuration, if their corresponding valid bit is zero.
1155 * fetch configuration to be programmed into the rx_fetch_size field of the
1158 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1161 * of the host, requesting configuration of the receive channel.
1173 * configuration to be programmed into the priority field of the channel's
1177 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1184 * host, requesting configuration of the receive channel.
1186 * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1195 * subordinate of the host, requesting configuration of the receive channel.
1197 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1202 * interpretation configuration to be programmed into the rx_atype field of the
1206 * mechanism configuration to be programmed into the rx_chan_type field of the
1209 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1212 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1215 * @rx_burst_size: UDMAP receive channel burst size configuration to be
1243 * Configuration does not include the flow registers which handle size-based
1247 * the RM board configuration resource assignment range list.
1252 * Bitfield defining validity of rx flow configuration parameters. The
1253 * rx flow configuration fields are not valid, and will not be used for flow
1254 * configuration, if their corresponding valid bit is zero. Valid bit usage:
1278 * @flow_index: UDMAP receive flow index for non-optional configuration.
1281 * UDMAP receive flow extended packet info present configuration to be
1285 * UDMAP receive flow PS words present configuration to be programmed into the
1289 * UDMAP receive flow error handling configuration to be programmed into the
1293 * UDMAP receive flow descriptor type configuration to be programmed into the
1297 * UDMAP receive flow start of packet offset configuration to be programmed
1303 * UDMAP receive flow destination queue configuration to be programmed into the
1307 * configuration of the receive flow.
1310 * UDMAP receive flow source tag high byte constant configuration to be
1315 * UDMAP receive flow source tag low byte constant configuration to be
1320 * UDMAP receive flow destination tag high byte constant configuration to be
1325 * UDMAP receive flow destination tag low byte constant configuration to be
1330 * UDMAP receive flow source tag high byte selector configuration to be
1335 * UDMAP receive flow source tag low byte selector configuration to be
1340 * UDMAP receive flow destination tag high byte selector configuration to be
1345 * UDMAP receive flow destination tag low byte selector configuration to be
1350 * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1355 * configuration of the receive flow.
1358 * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1363 * configuration of the receive flow.
1366 * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1371 * configuration of the receive flow.
1374 * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1379 * configuration of the receive flow.
1382 * UDMAP receive flow PS words location configuration to be programmed into the
1458 * struct ti_sci_msg_req_set_config - Set Processor boot configuration