Lines Matching +full:partial +full:- +full:fpga +full:- +full:config
1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
15 config FPGA_MGR_SOCFPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
21 config FPGA_MGR_SOCFPGA_A10
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
28 config ALTERA_PR_IP_CORE
29 tristate "Altera Partial Reconfiguration IP Core"
31 Core driver support for Altera Partial Reconfiguration IP component
33 config ALTERA_PR_IP_CORE_PLAT
34 tristate "Platform support of Altera Partial Reconfiguration IP Core"
37 Platform driver support for Altera Partial Reconfiguration IP
40 config FPGA_MGR_ALTERA_PS_SPI
41 tristate "Altera FPGA Passive Serial over SPI"
45 FPGA manager driver support for Altera Arria/Cyclone/Stratix
48 config FPGA_MGR_ALTERA_CVP
49 tristate "Altera CvP FPGA Manager"
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
55 config FPGA_MGR_ZYNQ_FPGA
56 tristate "Xilinx Zynq FPGA"
59 FPGA manager driver support for Xilinx Zynq FPGAs.
61 config FPGA_MGR_STRATIX10_SOC
62 tristate "Intel Stratix10 SoC FPGA Manager"
65 FPGA manager driver support for the Intel Stratix10 SoC.
67 config FPGA_MGR_XILINX_CORE
70 config FPGA_MGR_XILINX_SELECTMAP
75 FPGA manager driver support for Xilinx FPGA configuration
78 config FPGA_MGR_XILINX_SPI
83 FPGA manager driver support for Xilinx FPGA configuration
86 config FPGA_MGR_ICE40_SPI
90 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
92 config FPGA_MGR_MACHXO2_SPI
96 FPGA manager driver support for Lattice MachXO2 configuration
99 config FPGA_MGR_TS73XX
100 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
103 FPGA manager driver support for the Altera Cyclone II FPGA
104 present on the TS-73xx SBC boards.
106 config FPGA_BRIDGE
107 tristate "FPGA Bridge Framework"
112 config SOCFPGA_FPGA_BRIDGE
113 tristate "Altera SoCFPGA FPGA Bridges"
116 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
119 config ALTERA_FREEZE_BRIDGE
120 tristate "Altera FPGA Freeze Bridge"
123 Say Y to enable drivers for Altera FPGA Freeze bridges. A
124 freeze bridge is a bridge that exists in the FPGA fabric to
125 isolate one region of the FPGA from the busses while that
128 config XILINX_PR_DECOUPLER
135 The PR Decoupler exists in the FPGA fabric to isolate one
136 region of the FPGA from the busses while that region is
137 being reprogrammed during partial reconfig.
140 safely handles AXI4MM and AXI4-Lite interfaces on a
145 config FPGA_REGION
146 tristate "FPGA Region"
149 FPGA Region common code. An FPGA Region controls an FPGA Manager
150 and the FPGA Bridges associated with either a reconfigurable
151 region of an FPGA or a whole FPGA.
153 config OF_FPGA_REGION
154 tristate "FPGA Region Device Tree Overlay Support"
157 Support for loading FPGA images by applying a Device Tree
160 config FPGA_DFL
161 tristate "FPGA Device Feature List (DFL) support"
168 to provide an extensible way of adding features for FPGA.
170 devices (e.g. FPGA Management Engine, Port and Accelerator
171 Function Unit) and their private features for target FPGA devices.
173 Select this option to enable common support for Field-Programmable
174 Gate Array (FPGA) solutions which implement Device Feature List.
177 config FPGA_DFL_FME
178 tristate "FPGA DFL FME Driver"
181 The FPGA Management Engine (FME) is a feature device implemented
184 FPGA platform level management features. There shall be one FME
185 per DFL based FPGA device.
187 config FPGA_DFL_FME_MGR
188 tristate "FPGA DFL FME Manager Driver"
191 Say Y to enable FPGA Manager driver for FPGA Management Engine.
193 config FPGA_DFL_FME_BRIDGE
194 tristate "FPGA DFL FME Bridge Driver"
197 Say Y to enable FPGA Bridge driver for FPGA Management Engine.
199 config FPGA_DFL_FME_REGION
200 tristate "FPGA DFL FME Region Driver"
203 Say Y to enable FPGA Region driver for FPGA Management Engine.
205 config FPGA_DFL_AFU
206 tristate "FPGA DFL AFU Driver"
209 This is the driver for FPGA Accelerated Function Unit (AFU) which
211 to the FPGA infrastructure via a Port. There may be more than one
212 Port/AFU per DFL based FPGA device.
214 config FPGA_DFL_NIOS_INTEL_PAC_N3000
215 tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
222 the card. It also instantiates the SPI master (spi-altera) for
225 config FPGA_DFL_PCI
226 tristate "FPGA DFL PCIe Device Driver"
229 Select this option to enable PCIe driver for PCIe-based
230 Field-Programmable Gate Array (FPGA) solutions which implement
233 FPGA accelerators on the FPGA DFL devices, enables system level
234 management functions such as FPGA partial reconfiguration, power
240 config FPGA_MGR_ZYNQMP_FPGA
241 tristate "Xilinx ZynqMP FPGA"
244 FPGA manager driver support for Xilinx ZynqMP FPGAs.
249 config FPGA_MGR_VERSAL_FPGA
250 tristate "Xilinx Versal FPGA"
253 Select this option to enable FPGA manager driver support for
259 config FPGA_M10_BMC_SEC_UPDATE
270 the FPGA image, the Root Entry Hashes, etc.
272 config FPGA_MGR_MICROCHIP_SPI
273 tristate "Microchip Polarfire SPI FPGA manager"
276 FPGA manager driver support for Microchip Polarfire FPGAs
280 config FPGA_MGR_LATTICE_SYSCONFIG
283 config FPGA_MGR_LATTICE_SYSCONFIG_SPI
284 tristate "Lattice sysCONFIG SPI FPGA manager"
288 FPGA manager driver support for Lattice FPGAs programming over slave
291 source "drivers/fpga/tests/Kconfig"
293 endif # FPGA