1 // SPDX-License-Identifier: GPL-2.0
3  * KUnit test for the FPGA Manager
12 #include <linux/fpga/fpga-mgr.h>
42 	struct fpga_manager *mgr;  member
58  * init_test_buffer() - Allocate and initialize a test image in a buffer.
74 	memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE);  in init_test_buffer()
81  * since, in this case, it is a failure of the FPGA manager itself, not this
84 static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info,  in op_parse_header()  argument
87 	struct mgr_stats *stats = mgr->priv;  in op_parse_header()
90 	stats->op_parse_header_state = mgr->state;  in op_parse_header()
91 	stats->op_parse_header_seq = stats->seq_num++;  in op_parse_header()
94 	info->header_size = HEADER_SIZE;  in op_parse_header()
95 	info->data_size = info->count - HEADER_SIZE;  in op_parse_header()
97 	stats->header_match = true;  in op_parse_header()
98 	for (i = 0; i < info->header_size; i++) {  in op_parse_header()
100 			stats->header_match = false;  in op_parse_header()
108 static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info *info,  in op_write_init()  argument
111 	struct mgr_stats *stats = mgr->priv;  in op_write_init()
113 	stats->op_write_init_state = mgr->state;  in op_write_init()
114 	stats->op_write_init_seq = stats->seq_num++;  in op_write_init()
123 static int op_write(struct fpga_manager *mgr, const char *buf, size_t count)  in op_write()  argument
125 	struct mgr_stats *stats = mgr->priv;  in op_write()
128 	stats->op_write_state = mgr->state;  in op_write()
129 	stats->op_write_seq = stats->seq_num++;  in op_write()
131 	stats->image_match = true;  in op_write()
134 			stats->image_match = false;  in op_write()
147 static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt)  in op_write_sg()  argument
149 	struct mgr_stats *stats = mgr->priv;  in op_write_sg()
154 	stats->op_write_sg_state = mgr->state;  in op_write_sg()
155 	stats->op_write_sg_seq = stats->seq_num++;  in op_write_sg()
157 	stats->image_match = true;  in op_write_sg()
158 	sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);  in op_write_sg()
161 		stats->image_match = false;  in op_write_sg()
169 				stats->image_match = false;  in op_write_sg()
179 static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info)  in op_write_complete()  argument
181 	struct mgr_stats *stats = mgr->priv;  in op_write_complete()
183 	stats->op_write_complete_state = mgr->state;  in op_write_complete()
184 	stats->op_write_complete_seq = stats->seq_num++;  in op_write_complete()
190  * Fake FPGA manager that implements all ops required to check the programming
204 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_get()
205 	struct fpga_manager *mgr;  in fpga_mgr_test_get()  local
207 	mgr = fpga_mgr_get(ctx->dev);  in fpga_mgr_test_get()
208 	KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr);  in fpga_mgr_test_get()
210 	fpga_mgr_put(ctx->mgr);  in fpga_mgr_test_get()
215 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_lock()
218 	ret = fpga_mgr_lock(ctx->mgr);  in fpga_mgr_test_lock()
221 	ret = fpga_mgr_lock(ctx->mgr);  in fpga_mgr_test_lock()
222 	KUNIT_EXPECT_EQ(test, ret, -EBUSY);  in fpga_mgr_test_lock()
224 	fpga_mgr_unlock(ctx->mgr);  in fpga_mgr_test_lock()
230 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_img_load_buf()
236 	ctx->img_info->count = IMAGE_SIZE;  in fpga_mgr_test_img_load_buf()
237 	ctx->img_info->buf = img_buf;  in fpga_mgr_test_img_load_buf()
239 	ret = fpga_mgr_load(ctx->mgr, ctx->img_info);  in fpga_mgr_test_img_load_buf()
242 	KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);  in fpga_mgr_test_img_load_buf()
243 	KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);  in fpga_mgr_test_img_load_buf()
245 	KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);  in fpga_mgr_test_img_load_buf()
246 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);  in fpga_mgr_test_img_load_buf()
247 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE);  in fpga_mgr_test_img_load_buf()
248 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);  in fpga_mgr_test_img_load_buf()
250 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);  in fpga_mgr_test_img_load_buf()
251 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header_seq + 2);  in fpga_mgr_test_img_load_buf()
252 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);  in fpga_mgr_test_img_load_buf()
258 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_img_load_sgt()
268 	sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE);  in fpga_mgr_test_img_load_sgt()
273 	ctx->img_info->sgt = sgt;  in fpga_mgr_test_img_load_sgt()
275 	ret = fpga_mgr_load(ctx->mgr, ctx->img_info);  in fpga_mgr_test_img_load_sgt()
278 	KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);  in fpga_mgr_test_img_load_sgt()
279 	KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);  in fpga_mgr_test_img_load_sgt()
281 	KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);  in fpga_mgr_test_img_load_sgt()
282 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);  in fpga_mgr_test_img_load_sgt()
283 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE);  in fpga_mgr_test_img_load_sgt()
284 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);  in fpga_mgr_test_img_load_sgt()
286 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);  in fpga_mgr_test_img_load_sgt()
287 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_header_seq + 2);  in fpga_mgr_test_img_load_sgt()
288 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);  in fpga_mgr_test_img_load_sgt()
299 	ctx->dev = kunit_device_register(test, "fpga-manager-test-dev");  in fpga_mgr_test_init()
300 	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->dev);  in fpga_mgr_test_init()
302 	ctx->mgr = devm_fpga_mgr_register(ctx->dev, "Fake FPGA Manager", &fake_mgr_ops,  in fpga_mgr_test_init()
303 					  &ctx->stats);  in fpga_mgr_test_init()
304 	KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr));  in fpga_mgr_test_init()
306 	ctx->img_info = fpga_image_info_alloc(ctx->dev);  in fpga_mgr_test_init()
307 	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info);  in fpga_mgr_test_init()
309 	ret = kunit_add_action_or_reset(test, fpga_image_info_free_wrapper, ctx->img_info);  in fpga_mgr_test_init()
312 	test->priv = ctx;  in fpga_mgr_test_init()