Lines Matching defs:amdgpu_device
860 struct amdgpu_device { struct
861 struct device *dev;
862 struct pci_dev *pdev;
863 struct drm_device ddev;
866 struct amdgpu_acp acp;
868 struct amdgpu_hive_info *hive;
869 struct amdgpu_xcp_mgr *xcp_mgr;
871 enum amd_asic_type asic_type;
872 uint32_t family;
873 uint32_t rev_id;
874 uint32_t external_rev_id;
875 unsigned long flags;
876 unsigned long apu_flags;
877 int usec_timeout;
878 const struct amdgpu_asic_funcs *asic_funcs;
879 bool shutdown;
880 bool need_swiotlb;
881 bool accel_working;
882 struct notifier_block acpi_nb;
883 struct notifier_block pm_nb;
884 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
885 struct debugfs_blob_wrapper debugfs_vbios_blob;
886 struct debugfs_blob_wrapper debugfs_discovery_blob;
887 struct mutex srbm_mutex;
889 struct mutex grbm_idx_mutex;
890 struct dev_pm_domain vga_pm_domain;
891 bool have_disp_power_ref;
892 bool have_atomics_support;
895 bool is_atom_fw;
896 uint8_t *bios;
897 uint32_t bios_size;
898 uint32_t bios_scratch_reg_offset;
899 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
902 resource_size_t rmmio_base;
903 resource_size_t rmmio_size;
904 void __iomem *rmmio;
906 spinlock_t mmio_idx_lock;
907 struct amdgpu_mmio_remap rmmio_remap;
909 spinlock_t smc_idx_lock;
910 amdgpu_rreg_t smc_rreg;
911 amdgpu_wreg_t smc_wreg;
913 spinlock_t pcie_idx_lock;
914 amdgpu_rreg_t pcie_rreg;
915 amdgpu_wreg_t pcie_wreg;
916 amdgpu_rreg_t pciep_rreg;
917 amdgpu_wreg_t pciep_wreg;
918 amdgpu_rreg_ext_t pcie_rreg_ext;
919 amdgpu_wreg_ext_t pcie_wreg_ext;
920 amdgpu_rreg64_t pcie_rreg64;
921 amdgpu_wreg64_t pcie_wreg64;
922 amdgpu_rreg64_ext_t pcie_rreg64_ext;
923 amdgpu_wreg64_ext_t pcie_wreg64_ext;
925 spinlock_t uvd_ctx_idx_lock;
926 amdgpu_rreg_t uvd_ctx_rreg;
927 amdgpu_wreg_t uvd_ctx_wreg;
929 spinlock_t didt_idx_lock;
930 amdgpu_rreg_t didt_rreg;
931 amdgpu_wreg_t didt_wreg;
933 spinlock_t gc_cac_idx_lock;
934 amdgpu_rreg_t gc_cac_rreg;
935 amdgpu_wreg_t gc_cac_wreg;
937 spinlock_t se_cac_idx_lock;
938 amdgpu_rreg_t se_cac_rreg;
939 amdgpu_wreg_t se_cac_wreg;
941 spinlock_t audio_endpt_idx_lock;
942 amdgpu_block_rreg_t audio_endpt_rreg;
943 amdgpu_block_wreg_t audio_endpt_wreg;
944 struct amdgpu_doorbell doorbell;
947 struct amdgpu_clock clock;
950 struct amdgpu_gmc gmc;
951 struct amdgpu_gart gart;
952 dma_addr_t dummy_page_addr;
953 struct amdgpu_vm_manager vm_manager;
954 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
980 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ argument
981 struct delayed_work hotplug_work;
982 struct amdgpu_irq_src crtc_irq;
983 struct amdgpu_irq_src vline0_irq;
984 struct amdgpu_irq_src vupdate_irq;
985 struct amdgpu_irq_src pageflip_irq;
986 struct amdgpu_irq_src hpd_irq;
987 struct amdgpu_irq_src dmub_trace_irq;
988 struct amdgpu_irq_src dmub_outbox_irq;
991 u64 fence_context;
992 unsigned num_rings;
993 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
994 struct dma_fence __rcu *gang_submit;
995 bool ib_pool_ready;
996 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
997 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
1000 struct amdgpu_irq irq;
1003 struct amd_powerplay powerplay;
1004 struct amdgpu_pm pm;
1005 u64 cg_flags;
1006 u32 pg_flags;
1009 struct amdgpu_nbio nbio;
1012 struct amdgpu_hdp hdp;
1015 struct amdgpu_smuio smuio;
1018 struct amdgpu_mmhub mmhub;
1021 struct amdgpu_gfxhub gfxhub;
1024 struct amdgpu_gfx gfx;
1027 struct amdgpu_sdma sdma;
1030 struct amdgpu_lsdma lsdma;
1033 struct amdgpu_uvd uvd;
1036 struct amdgpu_vce vce;
1039 struct amdgpu_vcn vcn;
1042 struct amdgpu_jpeg jpeg;
1045 struct amdgpu_vpe vpe;
1048 struct amdgpu_umsch_mm umsch_mm;
1049 bool enable_umsch_mm;
1052 struct amdgpu_firmware firmware;
1055 struct psp_context psp;
1058 struct amdgpu_gds gds;
1061 struct amdgpu_seq64 seq64;
1064 struct amdgpu_kfd_dev kfd;
1067 struct amdgpu_umc umc;
1070 struct amdgpu_display_manager dm;
1074 struct amdgpu_isp isp;
1078 bool enable_mes;
1079 bool enable_mes_kiq;
1080 bool enable_uni_mes;
1081 struct amdgpu_mes mes;
1082 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1085 struct amdgpu_df df;
1088 struct amdgpu_mca mca;
1091 struct amdgpu_aca aca;
1093 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1094 uint32_t harvest_ip_mask;
1095 int num_ip_blocks;
1096 struct mutex mn_lock;
1100 atomic64_t vram_pin_size;
1101 atomic64_t visible_pin_size;
1102 atomic64_t gart_pin_size;
1105 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1106 struct amdgpu_ip_map_info ip_map;
1109 struct delayed_work delayed_init_work;
1111 struct amdgpu_virt virt;
1114 bool has_hw_reset;
1115 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1118 bool in_suspend;
1119 bool in_s3;
1120 bool in_s4;
1121 bool in_s0ix;
1123 enum pp_mp1_state mp1_state;
1124 struct amdgpu_doorbell_index doorbell_index;
1126 struct mutex notifier_lock;
1128 int asic_reset_res;
1129 struct work_struct xgmi_reset_work;
1130 struct list_head reset_list;
1132 long gfx_timeout;
1133 long sdma_timeout;
1134 long video_timeout;
1135 long compute_timeout;
1136 long psp_timeout;
1138 uint64_t unique_id;
1139 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1142 bool in_runpm;
1143 bool has_pr3;
1145 bool ucode_sysfs_en;
1147 struct amdgpu_fru_info *fru_info;
1148 atomic_t throttling_logging_enabled;
1149 struct ratelimit_state throttling_logging_rs;
1150 uint32_t ras_hw_enabled;
1151 uint32_t ras_enabled;
1153 bool no_hw_access;
1154 struct pci_saved_state *pci_state;
1155 pci_channel_state_t pci_channel_state;
1158 bool barrier_has_auto_waitcnt;
1160 struct amdgpu_reset_control *reset_cntl;
1161 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1163 bool ram_is_direct_mapped;
1165 struct list_head ras_list;
1167 struct ip_discovery_top *ip_top;
1169 struct amdgpu_reset_domain *reset_domain;
1171 struct mutex benchmark_mutex;
1173 bool scpm_enabled;
1197 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, in amdgpu_ip_version() argument