Lines Matching +full:gfx +full:- +full:mem
2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
247 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; in amdgpu_discovery_read_binary_from_sysmem()
249 /* This region is read-only and reserved from system use */ in amdgpu_discovery_read_binary_from_sysmem()
250 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); in amdgpu_discovery_read_binary_from_sysmem()
252 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); in amdgpu_discovery_read_binary_from_sysmem()
257 return -ENOENT; in amdgpu_discovery_read_binary_from_sysmem()
272 * but generally it should be in the 60-100ms range. Normally this starts in amdgpu_discovery_read_binary_from_mem()
290 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; in amdgpu_discovery_read_binary_from_mem()
292 adev->mman.discovery_tmr_size, false); in amdgpu_discovery_read_binary_from_mem()
311 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); in amdgpu_discovery_read_binary_from_file()
312 return -EINVAL; in amdgpu_discovery_read_binary_from_file()
315 r = request_firmware(&fw, fw_name, adev->dev); in amdgpu_discovery_read_binary_from_file()
317 dev_err(adev->dev, "can't load firmware \"%s\"\n", in amdgpu_discovery_read_binary_from_file()
322 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); in amdgpu_discovery_read_binary_from_file()
350 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); in amdgpu_discovery_verify_binary_signature()
361 switch (adev->pdev->revision) { in amdgpu_discovery_harvest_config_quirk()
369 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; in amdgpu_discovery_harvest_config_quirk()
370 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; in amdgpu_discovery_harvest_config_quirk()
385 info = &bhdr->table_list[NPS_INFO]; in amdgpu_discovery_verify_npsinfo()
386 offset = le16_to_cpu(info->offset); in amdgpu_discovery_verify_npsinfo()
387 checksum = le16_to_cpu(info->checksum); in amdgpu_discovery_verify_npsinfo()
390 (struct nps_info_header *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_verify_npsinfo()
392 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { in amdgpu_discovery_verify_npsinfo()
393 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); in amdgpu_discovery_verify_npsinfo()
394 return -EINVAL; in amdgpu_discovery_verify_npsinfo()
397 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, in amdgpu_discovery_verify_npsinfo()
398 le32_to_cpu(nhdr->size_bytes), in amdgpu_discovery_verify_npsinfo()
400 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); in amdgpu_discovery_verify_npsinfo()
401 return -EINVAL; in amdgpu_discovery_verify_npsinfo()
416 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; in amdgpu_discovery_init()
417 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); in amdgpu_discovery_init()
418 if (!adev->mman.discovery_bin) in amdgpu_discovery_init()
419 return -ENOMEM; in amdgpu_discovery_init()
423 dev_info(adev->dev, "use ip discovery information from file"); in amdgpu_discovery_init()
424 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); in amdgpu_discovery_init()
427 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); in amdgpu_discovery_init()
428 r = -EINVAL; in amdgpu_discovery_init()
434 adev, adev->mman.discovery_bin); in amdgpu_discovery_init()
440 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { in amdgpu_discovery_init()
441 dev_err(adev->dev, in amdgpu_discovery_init()
443 r = -EINVAL; in amdgpu_discovery_init()
447 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_init()
450 sizeof(bhdr->binary_checksum); in amdgpu_discovery_init()
451 size = le16_to_cpu(bhdr->binary_size) - offset; in amdgpu_discovery_init()
452 checksum = le16_to_cpu(bhdr->binary_checksum); in amdgpu_discovery_init()
454 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, in amdgpu_discovery_init()
456 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); in amdgpu_discovery_init()
457 r = -EINVAL; in amdgpu_discovery_init()
461 info = &bhdr->table_list[IP_DISCOVERY]; in amdgpu_discovery_init()
462 offset = le16_to_cpu(info->offset); in amdgpu_discovery_init()
463 checksum = le16_to_cpu(info->checksum); in amdgpu_discovery_init()
467 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_init()
468 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { in amdgpu_discovery_init()
469 dev_err(adev->dev, "invalid ip discovery data table signature\n"); in amdgpu_discovery_init()
470 r = -EINVAL; in amdgpu_discovery_init()
474 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, in amdgpu_discovery_init()
475 le16_to_cpu(ihdr->size), checksum)) { in amdgpu_discovery_init()
476 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); in amdgpu_discovery_init()
477 r = -EINVAL; in amdgpu_discovery_init()
482 info = &bhdr->table_list[GC]; in amdgpu_discovery_init()
483 offset = le16_to_cpu(info->offset); in amdgpu_discovery_init()
484 checksum = le16_to_cpu(info->checksum); in amdgpu_discovery_init()
488 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_init()
490 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { in amdgpu_discovery_init()
491 dev_err(adev->dev, "invalid ip discovery gc table id\n"); in amdgpu_discovery_init()
492 r = -EINVAL; in amdgpu_discovery_init()
496 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, in amdgpu_discovery_init()
497 le32_to_cpu(ghdr->size), checksum)) { in amdgpu_discovery_init()
498 dev_err(adev->dev, "invalid gc data table checksum\n"); in amdgpu_discovery_init()
499 r = -EINVAL; in amdgpu_discovery_init()
504 info = &bhdr->table_list[HARVEST_INFO]; in amdgpu_discovery_init()
505 offset = le16_to_cpu(info->offset); in amdgpu_discovery_init()
506 checksum = le16_to_cpu(info->checksum); in amdgpu_discovery_init()
510 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_init()
512 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { in amdgpu_discovery_init()
513 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); in amdgpu_discovery_init()
514 r = -EINVAL; in amdgpu_discovery_init()
518 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, in amdgpu_discovery_init()
520 dev_err(adev->dev, "invalid harvest data table checksum\n"); in amdgpu_discovery_init()
521 r = -EINVAL; in amdgpu_discovery_init()
526 info = &bhdr->table_list[VCN_INFO]; in amdgpu_discovery_init()
527 offset = le16_to_cpu(info->offset); in amdgpu_discovery_init()
528 checksum = le16_to_cpu(info->checksum); in amdgpu_discovery_init()
532 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_init()
534 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { in amdgpu_discovery_init()
535 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); in amdgpu_discovery_init()
536 r = -EINVAL; in amdgpu_discovery_init()
540 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, in amdgpu_discovery_init()
541 le32_to_cpu(vhdr->size_bytes), checksum)) { in amdgpu_discovery_init()
542 dev_err(adev->dev, "invalid vcn data table checksum\n"); in amdgpu_discovery_init()
543 r = -EINVAL; in amdgpu_discovery_init()
548 info = &bhdr->table_list[MALL_INFO]; in amdgpu_discovery_init()
549 offset = le16_to_cpu(info->offset); in amdgpu_discovery_init()
550 checksum = le16_to_cpu(info->checksum); in amdgpu_discovery_init()
554 (struct mall_info_header *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_init()
556 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { in amdgpu_discovery_init()
557 dev_err(adev->dev, "invalid ip discovery mall table id\n"); in amdgpu_discovery_init()
558 r = -EINVAL; in amdgpu_discovery_init()
562 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, in amdgpu_discovery_init()
563 le32_to_cpu(mhdr->size_bytes), checksum)) { in amdgpu_discovery_init()
564 dev_err(adev->dev, "invalid mall data table checksum\n"); in amdgpu_discovery_init()
565 r = -EINVAL; in amdgpu_discovery_init()
573 kfree(adev->mman.discovery_bin); in amdgpu_discovery_init()
574 adev->mman.discovery_bin = NULL; in amdgpu_discovery_init()
586 kfree(adev->mman.discovery_bin); in amdgpu_discovery_fini()
587 adev->mman.discovery_bin = NULL; in amdgpu_discovery_fini()
592 if (ip->instance_number >= HWIP_MAX_INSTANCE) { in amdgpu_discovery_validate_ip()
594 ip->instance_number); in amdgpu_discovery_validate_ip()
595 return -EINVAL; in amdgpu_discovery_validate_ip()
597 if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) { in amdgpu_discovery_validate_ip()
599 le16_to_cpu(ip->hw_id)); in amdgpu_discovery_validate_ip()
600 return -EINVAL; in amdgpu_discovery_validate_ip()
616 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_read_harvest_bit_per_ip()
617 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + in amdgpu_discovery_read_harvest_bit_per_ip()
618 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); in amdgpu_discovery_read_harvest_bit_per_ip()
619 num_dies = le16_to_cpu(ihdr->num_dies); in amdgpu_discovery_read_harvest_bit_per_ip()
623 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); in amdgpu_discovery_read_harvest_bit_per_ip()
624 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); in amdgpu_discovery_read_harvest_bit_per_ip()
625 num_ips = le16_to_cpu(dhdr->num_ips); in amdgpu_discovery_read_harvest_bit_per_ip()
629 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); in amdgpu_discovery_read_harvest_bit_per_ip()
634 if (le16_to_cpu(ip->variant) == 1) { in amdgpu_discovery_read_harvest_bit_per_ip()
635 switch (le16_to_cpu(ip->hw_id)) { in amdgpu_discovery_read_harvest_bit_per_ip()
638 if (ip->instance_number == 0) { in amdgpu_discovery_read_harvest_bit_per_ip()
639 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; in amdgpu_discovery_read_harvest_bit_per_ip()
640 adev->vcn.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
642 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
645 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; in amdgpu_discovery_read_harvest_bit_per_ip()
646 adev->vcn.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
648 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
653 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; in amdgpu_discovery_read_harvest_bit_per_ip()
660 if (ihdr->base_addr_64_bit) in amdgpu_discovery_read_harvest_bit_per_ip()
661 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); in amdgpu_discovery_read_harvest_bit_per_ip()
663 ip_offset += struct_size(ip, base_address, ip->num_base_address); in amdgpu_discovery_read_harvest_bit_per_ip()
678 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_read_from_harvest_table()
679 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); in amdgpu_discovery_read_from_harvest_table()
682 dev_err(adev->dev, "invalid harvest table offset\n"); in amdgpu_discovery_read_from_harvest_table()
686 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_read_from_harvest_table()
689 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) in amdgpu_discovery_read_from_harvest_table()
692 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { in amdgpu_discovery_read_from_harvest_table()
695 adev->vcn.harvest_config |= in amdgpu_discovery_read_from_harvest_table()
696 (1 << harvest_info->list[i].number_instance); in amdgpu_discovery_read_from_harvest_table()
697 adev->jpeg.harvest_config |= in amdgpu_discovery_read_from_harvest_table()
698 (1 << harvest_info->list[i].number_instance); in amdgpu_discovery_read_from_harvest_table()
700 adev->vcn.inst_mask &= in amdgpu_discovery_read_from_harvest_table()
701 ~(1U << harvest_info->list[i].number_instance); in amdgpu_discovery_read_from_harvest_table()
702 adev->jpeg.inst_mask &= in amdgpu_discovery_read_from_harvest_table()
703 ~(1U << harvest_info->list[i].number_instance); in amdgpu_discovery_read_from_harvest_table()
706 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; in amdgpu_discovery_read_from_harvest_table()
710 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); in amdgpu_discovery_read_from_harvest_table()
714 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
715 ~(1U << harvest_info->list[i].number_instance); in amdgpu_discovery_read_from_harvest_table()
718 adev->sdma.sdma_mask &= in amdgpu_discovery_read_from_harvest_table()
719 ~(1U << harvest_info->list[i].number_instance); in amdgpu_discovery_read_from_harvest_table()
723 adev->isp.harvest_config |= in amdgpu_discovery_read_from_harvest_table()
724 ~(1U << harvest_info->list[i].number_instance); in amdgpu_discovery_read_from_harvest_table()
732 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & in amdgpu_discovery_read_from_harvest_table()
760 /* -------------------------------------------------- */
769 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); in hw_id_show()
774 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); in num_instance_show()
779 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); in major_show()
784 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); in minor_show()
789 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); in revision_show()
794 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); in harvest_show()
799 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); in num_base_addresses_show()
807 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { in base_addr_show()
813 ip_hw_instance->base_addr[ii]); in base_addr_show()
846 if (!ip_hw_attr->show) in ip_hw_instance_attr_show()
847 return -EIO; in ip_hw_instance_attr_show()
849 return ip_hw_attr->show(ip_hw_instance, buf); in ip_hw_instance_attr_show()
869 /* -------------------------------------------------- */
877 if (!list_empty(&ip_hw_id->hw_id_kset.list)) in ip_hw_id_release()
878 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); in ip_hw_id_release()
887 /* -------------------------------------------------- */
901 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); in num_ips_show()
926 if (!ip_die_entry_attr->show) in ip_die_entry_attr_show()
927 return -EIO; in ip_die_entry_attr_show()
929 return ip_die_entry_attr->show(ip_die_entry, buf); in ip_die_entry_attr_show()
936 if (!list_empty(&ip_die_entry->ip_kset.list)) in ip_die_entry_release()
937 DRM_ERROR("ip_die_entry->ip_kset is not empty"); in ip_die_entry_release()
972 if (!list_empty(&ip_top->die_kset.list)) in die_kobj_release()
973 DRM_ERROR("ip_top->die_kset is not empty"); in die_kobj_release()
980 struct amdgpu_device *adev = ip_top->adev; in ip_disc_release()
982 adev->ip_top = NULL; in ip_disc_release()
994 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; in amdgpu_discovery_get_harvest_info()
997 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) in amdgpu_discovery_get_harvest_info()
1004 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1007 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; in amdgpu_discovery_get_harvest_info()
1036 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); in amdgpu_discovery_sysfs_ips()
1038 le16_to_cpu(ip->hw_id) != ii) in amdgpu_discovery_sysfs_ips()
1049 return -ENOMEM; in amdgpu_discovery_sysfs_ips()
1050 ip_hw_id->hw_id = ii; in amdgpu_discovery_sysfs_ips()
1052 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); in amdgpu_discovery_sysfs_ips()
1053 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; in amdgpu_discovery_sysfs_ips()
1054 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; in amdgpu_discovery_sysfs_ips()
1055 res = kset_register(&ip_hw_id->hw_id_kset); in amdgpu_discovery_sysfs_ips()
1062 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, in amdgpu_discovery_sysfs_ips()
1063 &ip_hw_id->hw_id_kset.kobj, in amdgpu_discovery_sysfs_ips()
1068 kobject_name(&ip_die_entry->ip_kset.kobj)); in amdgpu_discovery_sysfs_ips()
1077 ip->num_base_address), in amdgpu_discovery_sysfs_ips()
1081 return -ENOMEM; in amdgpu_discovery_sysfs_ips()
1083 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ in amdgpu_discovery_sysfs_ips()
1084 ip_hw_instance->num_instance = ip->instance_number; in amdgpu_discovery_sysfs_ips()
1085 ip_hw_instance->major = ip->major; in amdgpu_discovery_sysfs_ips()
1086 ip_hw_instance->minor = ip->minor; in amdgpu_discovery_sysfs_ips()
1087 ip_hw_instance->revision = ip->revision; in amdgpu_discovery_sysfs_ips()
1088 ip_hw_instance->harvest = in amdgpu_discovery_sysfs_ips()
1090 adev, ip_hw_instance->hw_id, in amdgpu_discovery_sysfs_ips()
1091 ip_hw_instance->num_instance); in amdgpu_discovery_sysfs_ips()
1092 ip_hw_instance->num_base_addresses = ip->num_base_address; in amdgpu_discovery_sysfs_ips()
1094 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { in amdgpu_discovery_sysfs_ips()
1096 ip_hw_instance->base_addr[kk] = in amdgpu_discovery_sysfs_ips()
1097 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; in amdgpu_discovery_sysfs_ips()
1099 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; in amdgpu_discovery_sysfs_ips()
1102 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); in amdgpu_discovery_sysfs_ips()
1103 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; in amdgpu_discovery_sysfs_ips()
1104 res = kobject_add(&ip_hw_instance->kobj, NULL, in amdgpu_discovery_sysfs_ips()
1105 "%d", ip_hw_instance->num_instance); in amdgpu_discovery_sysfs_ips()
1109 ip->num_base_address); in amdgpu_discovery_sysfs_ips()
1112 ip->num_base_address); in amdgpu_discovery_sysfs_ips()
1124 struct kset *die_kset = &adev->ip_top->die_kset; in amdgpu_discovery_sysfs_recurse()
1129 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_sysfs_recurse()
1130 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + in amdgpu_discovery_sysfs_recurse()
1131 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); in amdgpu_discovery_sysfs_recurse()
1132 num_dies = le16_to_cpu(ihdr->num_dies); in amdgpu_discovery_sysfs_recurse()
1139 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); in amdgpu_discovery_sysfs_recurse()
1140 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); in amdgpu_discovery_sysfs_recurse()
1141 num_ips = le16_to_cpu(dhdr->num_ips); in amdgpu_discovery_sysfs_recurse()
1146 * dhdr->die_id == ii, which was checked in in amdgpu_discovery_sysfs_recurse()
1152 return -ENOMEM; in amdgpu_discovery_sysfs_recurse()
1154 ip_die_entry->num_ips = num_ips; in amdgpu_discovery_sysfs_recurse()
1156 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); in amdgpu_discovery_sysfs_recurse()
1157 ip_die_entry->ip_kset.kobj.kset = die_kset; in amdgpu_discovery_sysfs_recurse()
1158 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; in amdgpu_discovery_sysfs_recurse()
1159 res = kset_register(&ip_die_entry->ip_kset); in amdgpu_discovery_sysfs_recurse()
1166 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); in amdgpu_discovery_sysfs_recurse()
1177 if (!adev->mman.discovery_bin) in amdgpu_discovery_sysfs_init()
1178 return -EINVAL; in amdgpu_discovery_sysfs_init()
1180 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); in amdgpu_discovery_sysfs_init()
1181 if (!adev->ip_top) in amdgpu_discovery_sysfs_init()
1182 return -ENOMEM; in amdgpu_discovery_sysfs_init()
1184 adev->ip_top->adev = adev; in amdgpu_discovery_sysfs_init()
1186 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, in amdgpu_discovery_sysfs_init()
1187 &adev->dev->kobj, "ip_discovery"); in amdgpu_discovery_sysfs_init()
1193 die_kset = &adev->ip_top->die_kset; in amdgpu_discovery_sysfs_init()
1194 kobject_set_name(&die_kset->kobj, "%s", "die"); in amdgpu_discovery_sysfs_init()
1195 die_kset->kobj.parent = &adev->ip_top->kobj; in amdgpu_discovery_sysfs_init()
1196 die_kset->kobj.ktype = &die_kobj_ktype; in amdgpu_discovery_sysfs_init()
1197 res = kset_register(&adev->ip_top->die_kset); in amdgpu_discovery_sysfs_init()
1211 kobject_put(&adev->ip_top->kobj); in amdgpu_discovery_sysfs_init()
1215 /* -------------------------------------------------- */
1224 hw_id_kset = &ip_hw_id->hw_id_kset; in amdgpu_discovery_sysfs_ip_hw_free()
1225 spin_lock(&hw_id_kset->list_lock); in amdgpu_discovery_sysfs_ip_hw_free()
1226 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { in amdgpu_discovery_sysfs_ip_hw_free()
1228 spin_unlock(&hw_id_kset->list_lock); in amdgpu_discovery_sysfs_ip_hw_free()
1231 spin_lock(&hw_id_kset->list_lock); in amdgpu_discovery_sysfs_ip_hw_free()
1233 spin_unlock(&hw_id_kset->list_lock); in amdgpu_discovery_sysfs_ip_hw_free()
1234 kobject_put(&ip_hw_id->hw_id_kset.kobj); in amdgpu_discovery_sysfs_ip_hw_free()
1242 ip_kset = &ip_die_entry->ip_kset; in amdgpu_discovery_sysfs_die_free()
1243 spin_lock(&ip_kset->list_lock); in amdgpu_discovery_sysfs_die_free()
1244 list_for_each_prev_safe(el, tmp, &ip_kset->list) { in amdgpu_discovery_sysfs_die_free()
1246 spin_unlock(&ip_kset->list_lock); in amdgpu_discovery_sysfs_die_free()
1248 spin_lock(&ip_kset->list_lock); in amdgpu_discovery_sysfs_die_free()
1250 spin_unlock(&ip_kset->list_lock); in amdgpu_discovery_sysfs_die_free()
1251 kobject_put(&ip_die_entry->ip_kset.kobj); in amdgpu_discovery_sysfs_die_free()
1259 die_kset = &adev->ip_top->die_kset; in amdgpu_discovery_sysfs_fini()
1260 spin_lock(&die_kset->list_lock); in amdgpu_discovery_sysfs_fini()
1261 list_for_each_prev_safe(el, tmp, &die_kset->list) { in amdgpu_discovery_sysfs_fini()
1263 spin_unlock(&die_kset->list_lock); in amdgpu_discovery_sysfs_fini()
1265 spin_lock(&die_kset->list_lock); in amdgpu_discovery_sysfs_fini()
1267 spin_unlock(&die_kset->list_lock); in amdgpu_discovery_sysfs_fini()
1268 kobject_put(&adev->ip_top->die_kset.kobj); in amdgpu_discovery_sysfs_fini()
1269 kobject_put(&adev->ip_top->kobj); in amdgpu_discovery_sysfs_fini()
1295 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1296 adev->sdma.sdma_mask = 0; in amdgpu_discovery_reg_base_init()
1297 adev->vcn.inst_mask = 0; in amdgpu_discovery_reg_base_init()
1298 adev->jpeg.inst_mask = 0; in amdgpu_discovery_reg_base_init()
1299 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_reg_base_init()
1300 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + in amdgpu_discovery_reg_base_init()
1301 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); in amdgpu_discovery_reg_base_init()
1302 num_dies = le16_to_cpu(ihdr->num_dies); in amdgpu_discovery_reg_base_init()
1307 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); in amdgpu_discovery_reg_base_init()
1308 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); in amdgpu_discovery_reg_base_init()
1309 num_ips = le16_to_cpu(dhdr->num_ips); in amdgpu_discovery_reg_base_init()
1312 if (le16_to_cpu(dhdr->die_id) != i) { in amdgpu_discovery_reg_base_init()
1314 le16_to_cpu(dhdr->die_id), i); in amdgpu_discovery_reg_base_init()
1315 return -EINVAL; in amdgpu_discovery_reg_base_init()
1319 le16_to_cpu(dhdr->die_id), num_ips); in amdgpu_discovery_reg_base_init()
1322 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); in amdgpu_discovery_reg_base_init()
1327 num_base_address = ip->num_base_address; in amdgpu_discovery_reg_base_init()
1330 hw_id_names[le16_to_cpu(ip->hw_id)], in amdgpu_discovery_reg_base_init()
1331 le16_to_cpu(ip->hw_id), in amdgpu_discovery_reg_base_init()
1332 ip->instance_number, in amdgpu_discovery_reg_base_init()
1333 ip->major, ip->minor, in amdgpu_discovery_reg_base_init()
1334 ip->revision); in amdgpu_discovery_reg_base_init()
1336 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { in amdgpu_discovery_reg_base_init()
1343 if (adev->vcn.num_vcn_inst < in amdgpu_discovery_reg_base_init()
1345 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = in amdgpu_discovery_reg_base_init()
1346 ip->revision & 0xc0; in amdgpu_discovery_reg_base_init()
1347 adev->vcn.num_vcn_inst++; in amdgpu_discovery_reg_base_init()
1348 adev->vcn.inst_mask |= in amdgpu_discovery_reg_base_init()
1349 (1U << ip->instance_number); in amdgpu_discovery_reg_base_init()
1350 adev->jpeg.inst_mask |= in amdgpu_discovery_reg_base_init()
1351 (1U << ip->instance_number); in amdgpu_discovery_reg_base_init()
1353 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", in amdgpu_discovery_reg_base_init()
1354 adev->vcn.num_vcn_inst + 1, in amdgpu_discovery_reg_base_init()
1357 ip->revision &= ~0xc0; in amdgpu_discovery_reg_base_init()
1359 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || in amdgpu_discovery_reg_base_init()
1360 le16_to_cpu(ip->hw_id) == SDMA1_HWID || in amdgpu_discovery_reg_base_init()
1361 le16_to_cpu(ip->hw_id) == SDMA2_HWID || in amdgpu_discovery_reg_base_init()
1362 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { in amdgpu_discovery_reg_base_init()
1363 if (adev->sdma.num_instances < in amdgpu_discovery_reg_base_init()
1365 adev->sdma.num_instances++; in amdgpu_discovery_reg_base_init()
1366 adev->sdma.sdma_mask |= in amdgpu_discovery_reg_base_init()
1367 (1U << ip->instance_number); in amdgpu_discovery_reg_base_init()
1369 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", in amdgpu_discovery_reg_base_init()
1370 adev->sdma.num_instances + 1, in amdgpu_discovery_reg_base_init()
1375 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { in amdgpu_discovery_reg_base_init()
1376 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) in amdgpu_discovery_reg_base_init()
1377 adev->vpe.num_instances++; in amdgpu_discovery_reg_base_init()
1379 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", in amdgpu_discovery_reg_base_init()
1380 adev->vpe.num_instances + 1, in amdgpu_discovery_reg_base_init()
1384 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { in amdgpu_discovery_reg_base_init()
1385 adev->gmc.num_umc++; in amdgpu_discovery_reg_base_init()
1386 adev->umc.node_inst_num++; in amdgpu_discovery_reg_base_init()
1389 if (le16_to_cpu(ip->hw_id) == GC_HWID) in amdgpu_discovery_reg_base_init()
1390 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
1391 (1U << ip->instance_number); in amdgpu_discovery_reg_base_init()
1396 * so that we don't need to convert them when accessing adev->reg_offset. in amdgpu_discovery_reg_base_init()
1398 if (ihdr->base_addr_64_bit) in amdgpu_discovery_reg_base_init()
1408 ip->base_address[k] = in amdgpu_discovery_reg_base_init()
1409 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; in amdgpu_discovery_reg_base_init()
1411 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); in amdgpu_discovery_reg_base_init()
1412 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); in amdgpu_discovery_reg_base_init()
1416 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && in amdgpu_discovery_reg_base_init()
1419 hw_id_names[le16_to_cpu(ip->hw_id)]); in amdgpu_discovery_reg_base_init()
1420 adev->reg_offset[hw_ip][ip->instance_number] = in amdgpu_discovery_reg_base_init()
1421 ip->base_address; in amdgpu_discovery_reg_base_init()
1432 if (ihdr->version < 3) { in amdgpu_discovery_reg_base_init()
1436 subrev = ip->sub_revision; in amdgpu_discovery_reg_base_init()
1437 variant = ip->variant; in amdgpu_discovery_reg_base_init()
1440 adev->ip_versions[hw_ip] in amdgpu_discovery_reg_base_init()
1441 [ip->instance_number] = in amdgpu_discovery_reg_base_init()
1442 IP_VERSION_FULL(ip->major, in amdgpu_discovery_reg_base_init()
1443 ip->minor, in amdgpu_discovery_reg_base_init()
1444 ip->revision, in amdgpu_discovery_reg_base_init()
1451 if (ihdr->base_addr_64_bit) in amdgpu_discovery_reg_base_init()
1452 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); in amdgpu_discovery_reg_base_init()
1454 ip_offset += struct_size(ip, base_address, ip->num_base_address); in amdgpu_discovery_reg_base_init()
1474 if ((adev->pdev->device == 0x731E && in amdgpu_discovery_harvest_ip()
1475 (adev->pdev->revision == 0xC6 || in amdgpu_discovery_harvest_ip()
1476 adev->pdev->revision == 0xC7)) || in amdgpu_discovery_harvest_ip()
1477 (adev->pdev->device == 0x7340 && in amdgpu_discovery_harvest_ip()
1478 adev->pdev->revision == 0xC9) || in amdgpu_discovery_harvest_ip()
1479 (adev->pdev->device == 0x7360 && in amdgpu_discovery_harvest_ip()
1480 adev->pdev->revision == 0xC7)) in amdgpu_discovery_harvest_ip()
1491 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { in amdgpu_discovery_harvest_ip()
1492 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; in amdgpu_discovery_harvest_ip()
1493 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; in amdgpu_discovery_harvest_ip()
1496 if (umc_harvest_count < adev->gmc.num_umc) { in amdgpu_discovery_harvest_ip()
1497 adev->gmc.num_umc -= umc_harvest_count; in amdgpu_discovery_harvest_ip()
1516 if (!adev->mman.discovery_bin) { in amdgpu_discovery_get_gfx_info()
1518 return -EINVAL; in amdgpu_discovery_get_gfx_info()
1521 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_get_gfx_info()
1522 offset = le16_to_cpu(bhdr->table_list[GC].offset); in amdgpu_discovery_get_gfx_info()
1527 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_get_gfx_info()
1529 switch (le16_to_cpu(gc_info->v1.header.version_major)) { in amdgpu_discovery_get_gfx_info()
1531 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
1532 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
1533 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); in amdgpu_discovery_get_gfx_info()
1534 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1535 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1536 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
1537 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
1538 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
1539 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
1540 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
1541 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
1542 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); in amdgpu_discovery_get_gfx_info()
1543 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); in amdgpu_discovery_get_gfx_info()
1544 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); in amdgpu_discovery_get_gfx_info()
1545 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); in amdgpu_discovery_get_gfx_info()
1546 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / in amdgpu_discovery_get_gfx_info()
1547 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1548 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); in amdgpu_discovery_get_gfx_info()
1549 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { in amdgpu_discovery_get_gfx_info()
1550 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); in amdgpu_discovery_get_gfx_info()
1551 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); in amdgpu_discovery_get_gfx_info()
1552 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); in amdgpu_discovery_get_gfx_info()
1554 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { in amdgpu_discovery_get_gfx_info()
1555 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); in amdgpu_discovery_get_gfx_info()
1556 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); in amdgpu_discovery_get_gfx_info()
1557 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); in amdgpu_discovery_get_gfx_info()
1558 …adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instructio… in amdgpu_discovery_get_gfx_info()
1559 …adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_p… in amdgpu_discovery_get_gfx_info()
1560 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); in amdgpu_discovery_get_gfx_info()
1561 … adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); in amdgpu_discovery_get_gfx_info()
1562 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); in amdgpu_discovery_get_gfx_info()
1564 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { in amdgpu_discovery_get_gfx_info()
1565 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); in amdgpu_discovery_get_gfx_info()
1566 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); in amdgpu_discovery_get_gfx_info()
1567 …adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cach… in amdgpu_discovery_get_gfx_info()
1568 …adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_l… in amdgpu_discovery_get_gfx_info()
1569 …adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cach… in amdgpu_discovery_get_gfx_info()
1570 …adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_l… in amdgpu_discovery_get_gfx_info()
1571 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); in amdgpu_discovery_get_gfx_info()
1572 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); in amdgpu_discovery_get_gfx_info()
1576 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); in amdgpu_discovery_get_gfx_info()
1577 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); in amdgpu_discovery_get_gfx_info()
1578 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
1579 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1580 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); in amdgpu_discovery_get_gfx_info()
1581 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
1582 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
1583 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
1584 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
1585 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
1586 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); in amdgpu_discovery_get_gfx_info()
1587 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); in amdgpu_discovery_get_gfx_info()
1588 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); in amdgpu_discovery_get_gfx_info()
1589 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); in amdgpu_discovery_get_gfx_info()
1590 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / in amdgpu_discovery_get_gfx_info()
1591 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
1592 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); in amdgpu_discovery_get_gfx_info()
1593 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { in amdgpu_discovery_get_gfx_info()
1594 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); in amdgpu_discovery_get_gfx_info()
1595 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); in amdgpu_discovery_get_gfx_info()
1596 …adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XC… in amdgpu_discovery_get_gfx_info()
1597 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); in amdgpu_discovery_get_gfx_info()
1598 …adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_c… in amdgpu_discovery_get_gfx_info()
1599 …adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_si… in amdgpu_discovery_get_gfx_info()
1600 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ in amdgpu_discovery_get_gfx_info()
1604 dev_err(adev->dev, in amdgpu_discovery_get_gfx_info()
1606 le16_to_cpu(gc_info->v1.header.version_major), in amdgpu_discovery_get_gfx_info()
1607 le16_to_cpu(gc_info->v1.header.version_minor)); in amdgpu_discovery_get_gfx_info()
1608 return -EINVAL; in amdgpu_discovery_get_gfx_info()
1626 if (!adev->mman.discovery_bin) { in amdgpu_discovery_get_mall_info()
1628 return -EINVAL; in amdgpu_discovery_get_mall_info()
1631 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_get_mall_info()
1632 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); in amdgpu_discovery_get_mall_info()
1637 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_get_mall_info()
1639 switch (le16_to_cpu(mall_info->v1.header.version_major)) { in amdgpu_discovery_get_mall_info()
1642 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); in amdgpu_discovery_get_mall_info()
1643 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); in amdgpu_discovery_get_mall_info()
1644 half_use = le32_to_cpu(mall_info->v1.m_half_use); in amdgpu_discovery_get_mall_info()
1645 for (u = 0; u < adev->gmc.num_umc; u++) { in amdgpu_discovery_get_mall_info()
1653 adev->gmc.mall_size = mall_size; in amdgpu_discovery_get_mall_info()
1654 adev->gmc.m_half_use = half_use; in amdgpu_discovery_get_mall_info()
1657 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); in amdgpu_discovery_get_mall_info()
1658 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; in amdgpu_discovery_get_mall_info()
1661 dev_err(adev->dev, in amdgpu_discovery_get_mall_info()
1663 le16_to_cpu(mall_info->v1.header.version_major), in amdgpu_discovery_get_mall_info()
1664 le16_to_cpu(mall_info->v1.header.version_minor)); in amdgpu_discovery_get_mall_info()
1665 return -EINVAL; in amdgpu_discovery_get_mall_info()
1681 if (!adev->mman.discovery_bin) { in amdgpu_discovery_get_vcn_info()
1683 return -EINVAL; in amdgpu_discovery_get_vcn_info()
1691 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { in amdgpu_discovery_get_vcn_info()
1692 dev_err(adev->dev, "invalid vcn instances\n"); in amdgpu_discovery_get_vcn_info()
1693 return -EINVAL; in amdgpu_discovery_get_vcn_info()
1696 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_get_vcn_info()
1697 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); in amdgpu_discovery_get_vcn_info()
1702 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_get_vcn_info()
1704 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { in amdgpu_discovery_get_vcn_info()
1709 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { in amdgpu_discovery_get_vcn_info()
1710 adev->vcn.inst[v].vcn_codec_disable_mask = in amdgpu_discovery_get_vcn_info()
1711 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); in amdgpu_discovery_get_vcn_info()
1715 dev_err(adev->dev, in amdgpu_discovery_get_vcn_info()
1717 le16_to_cpu(vcn_info->v1.header.version_major), in amdgpu_discovery_get_vcn_info()
1718 le16_to_cpu(vcn_info->v1.header.version_minor)); in amdgpu_discovery_get_vcn_info()
1719 return -EINVAL; in amdgpu_discovery_get_vcn_info()
1737 pos = vram_size - DISCOVERY_TMR_OFFSET; in amdgpu_discovery_refresh_nps_info()
1748 le32_to_cpu(nhdr->size_bytes), in amdgpu_discovery_refresh_nps_info()
1750 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); in amdgpu_discovery_refresh_nps_info()
1751 return -EINVAL; in amdgpu_discovery_refresh_nps_info()
1770 return -EINVAL; in amdgpu_discovery_get_nps_info()
1778 if (!adev->mman.discovery_bin) { in amdgpu_discovery_get_nps_info()
1779 dev_err(adev->dev, in amdgpu_discovery_get_nps_info()
1780 "fetch mem range failed, ip discovery uninitialized\n"); in amdgpu_discovery_get_nps_info()
1781 return -EINVAL; in amdgpu_discovery_get_nps_info()
1784 bhdr = (struct binary_header *)adev->mman.discovery_bin; in amdgpu_discovery_get_nps_info()
1785 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); in amdgpu_discovery_get_nps_info()
1788 return -ENOENT; in amdgpu_discovery_get_nps_info()
1792 return -ENOENT; in amdgpu_discovery_get_nps_info()
1795 (union nps_info *)(adev->mman.discovery_bin + offset); in amdgpu_discovery_get_nps_info()
1798 switch (le16_to_cpu(nps_info->v1.header.version_major)) { in amdgpu_discovery_get_nps_info()
1800 mem_ranges = kvcalloc(nps_info->v1.count, in amdgpu_discovery_get_nps_info()
1804 return -ENOMEM; in amdgpu_discovery_get_nps_info()
1805 *nps_type = nps_info->v1.nps_type; in amdgpu_discovery_get_nps_info()
1806 *range_cnt = nps_info->v1.count; in amdgpu_discovery_get_nps_info()
1809 nps_info->v1.instance_info[i].base_address; in amdgpu_discovery_get_nps_info()
1811 nps_info->v1.instance_info[i].limit_address; in amdgpu_discovery_get_nps_info()
1812 mem_ranges[i].nid_mask = -1; in amdgpu_discovery_get_nps_info()
1818 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", in amdgpu_discovery_get_nps_info()
1819 le16_to_cpu(nps_info->v1.header.version_major), in amdgpu_discovery_get_nps_info()
1820 le16_to_cpu(nps_info->v1.header.version_minor)); in amdgpu_discovery_get_nps_info()
1821 return -EINVAL; in amdgpu_discovery_get_nps_info()
1874 dev_err(adev->dev, in amdgpu_discovery_set_common_ip_blocks()
1877 return -EINVAL; in amdgpu_discovery_set_common_ip_blocks()
1929 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", in amdgpu_discovery_set_gmc_ip_blocks()
1931 return -EINVAL; in amdgpu_discovery_set_gmc_ip_blocks()
1973 dev_err(adev->dev, in amdgpu_discovery_set_ih_ip_blocks()
1976 return -EINVAL; in amdgpu_discovery_set_ih_ip_blocks()
2035 dev_err(adev->dev, in amdgpu_discovery_set_psp_ip_blocks()
2038 return -EINVAL; in amdgpu_discovery_set_psp_ip_blocks()
2050 if (adev->asic_type == CHIP_ARCTURUS) in amdgpu_discovery_set_smu_ip_blocks()
2092 dev_err(adev->dev, in amdgpu_discovery_set_smu_ip_blocks()
2095 return -EINVAL; in amdgpu_discovery_set_smu_ip_blocks()
2110 if (adev->enable_virtual_display) { in amdgpu_discovery_set_display_ip_blocks()
2142 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) in amdgpu_discovery_set_display_ip_blocks()
2143 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_display_ip_blocks()
2151 dev_err(adev->dev, in amdgpu_discovery_set_display_ip_blocks()
2154 return -EINVAL; in amdgpu_discovery_set_display_ip_blocks()
2167 dev_err(adev->dev, in amdgpu_discovery_set_display_ip_blocks()
2170 return -EINVAL; in amdgpu_discovery_set_display_ip_blocks()
2225 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", in amdgpu_discovery_set_gc_ip_blocks()
2227 return -EINVAL; in amdgpu_discovery_set_gc_ip_blocks()
2280 dev_err(adev->dev, in amdgpu_discovery_set_sdma_ip_blocks()
2283 return -EINVAL; in amdgpu_discovery_set_sdma_ip_blocks()
2294 /* UVD is not supported on vega20 SR-IOV */ in amdgpu_discovery_set_mm_ip_blocks()
2295 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) in amdgpu_discovery_set_mm_ip_blocks()
2299 dev_err(adev->dev, in amdgpu_discovery_set_mm_ip_blocks()
2302 return -EINVAL; in amdgpu_discovery_set_mm_ip_blocks()
2307 /* VCE is not supported on vega20 SR-IOV */ in amdgpu_discovery_set_mm_ip_blocks()
2308 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) in amdgpu_discovery_set_mm_ip_blocks()
2312 dev_err(adev->dev, in amdgpu_discovery_set_mm_ip_blocks()
2315 return -EINVAL; in amdgpu_discovery_set_mm_ip_blocks()
2376 dev_err(adev->dev, in amdgpu_discovery_set_mm_ip_blocks()
2379 return -EINVAL; in amdgpu_discovery_set_mm_ip_blocks()
2397 adev->enable_mes = true; in amdgpu_discovery_set_mes_ip_blocks()
2398 adev->enable_mes_kiq = true; in amdgpu_discovery_set_mes_ip_blocks()
2403 adev->enable_mes = true; in amdgpu_discovery_set_mes_ip_blocks()
2404 adev->enable_mes_kiq = true; in amdgpu_discovery_set_mes_ip_blocks()
2406 adev->enable_uni_mes = true; in amdgpu_discovery_set_mes_ip_blocks()
2449 adev->enable_umsch_mm = true; in amdgpu_discovery_set_umsch_mm_ip_blocks()
2481 switch (adev->asic_type) { in amdgpu_discovery_set_ip_blocks()
2484 adev->sdma.num_instances = 2; in amdgpu_discovery_set_ip_blocks()
2485 adev->gmc.num_umc = 4; in amdgpu_discovery_set_ip_blocks()
2486 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2487 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2488 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2489 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2490 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2491 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2492 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); in amdgpu_discovery_set_ip_blocks()
2493 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); in amdgpu_discovery_set_ip_blocks()
2494 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); in amdgpu_discovery_set_ip_blocks()
2495 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2496 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2497 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2498 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2499 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); in amdgpu_discovery_set_ip_blocks()
2500 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2501 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2502 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); in amdgpu_discovery_set_ip_blocks()
2506 adev->sdma.num_instances = 2; in amdgpu_discovery_set_ip_blocks()
2507 adev->gmc.num_umc = 4; in amdgpu_discovery_set_ip_blocks()
2508 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); in amdgpu_discovery_set_ip_blocks()
2509 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); in amdgpu_discovery_set_ip_blocks()
2510 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
2511 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
2512 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
2513 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
2514 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); in amdgpu_discovery_set_ip_blocks()
2515 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); in amdgpu_discovery_set_ip_blocks()
2516 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); in amdgpu_discovery_set_ip_blocks()
2517 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2518 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2519 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2520 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); in amdgpu_discovery_set_ip_blocks()
2521 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); in amdgpu_discovery_set_ip_blocks()
2522 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2523 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2524 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); in amdgpu_discovery_set_ip_blocks()
2528 adev->sdma.num_instances = 1; in amdgpu_discovery_set_ip_blocks()
2529 adev->vcn.num_vcn_inst = 1; in amdgpu_discovery_set_ip_blocks()
2530 adev->gmc.num_umc = 2; in amdgpu_discovery_set_ip_blocks()
2531 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { in amdgpu_discovery_set_ip_blocks()
2532 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); in amdgpu_discovery_set_ip_blocks()
2533 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); in amdgpu_discovery_set_ip_blocks()
2534 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); in amdgpu_discovery_set_ip_blocks()
2535 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); in amdgpu_discovery_set_ip_blocks()
2536 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); in amdgpu_discovery_set_ip_blocks()
2537 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); in amdgpu_discovery_set_ip_blocks()
2538 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); in amdgpu_discovery_set_ip_blocks()
2539 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); in amdgpu_discovery_set_ip_blocks()
2540 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
2541 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
2542 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); in amdgpu_discovery_set_ip_blocks()
2543 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
2544 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); in amdgpu_discovery_set_ip_blocks()
2545 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); in amdgpu_discovery_set_ip_blocks()
2546 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); in amdgpu_discovery_set_ip_blocks()
2547 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); in amdgpu_discovery_set_ip_blocks()
2549 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); in amdgpu_discovery_set_ip_blocks()
2550 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); in amdgpu_discovery_set_ip_blocks()
2551 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()
2552 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()
2553 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()
2554 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); in amdgpu_discovery_set_ip_blocks()
2555 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2556 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2557 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
2558 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
2559 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
2560 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
2561 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); in amdgpu_discovery_set_ip_blocks()
2562 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); in amdgpu_discovery_set_ip_blocks()
2563 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); in amdgpu_discovery_set_ip_blocks()
2564 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); in amdgpu_discovery_set_ip_blocks()
2569 adev->sdma.num_instances = 2; in amdgpu_discovery_set_ip_blocks()
2570 adev->gmc.num_umc = 8; in amdgpu_discovery_set_ip_blocks()
2571 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); in amdgpu_discovery_set_ip_blocks()
2572 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); in amdgpu_discovery_set_ip_blocks()
2573 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
2574 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
2575 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
2576 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
2577 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); in amdgpu_discovery_set_ip_blocks()
2578 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); in amdgpu_discovery_set_ip_blocks()
2579 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); in amdgpu_discovery_set_ip_blocks()
2580 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2581 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2582 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2583 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2584 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); in amdgpu_discovery_set_ip_blocks()
2585 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); in amdgpu_discovery_set_ip_blocks()
2586 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); in amdgpu_discovery_set_ip_blocks()
2587 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()
2588 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); in amdgpu_discovery_set_ip_blocks()
2592 adev->sdma.num_instances = 8; in amdgpu_discovery_set_ip_blocks()
2593 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()
2594 adev->gmc.num_umc = 8; in amdgpu_discovery_set_ip_blocks()
2595 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); in amdgpu_discovery_set_ip_blocks()
2596 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); in amdgpu_discovery_set_ip_blocks()
2597 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); in amdgpu_discovery_set_ip_blocks()
2598 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); in amdgpu_discovery_set_ip_blocks()
2599 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2600 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2601 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2602 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2603 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2604 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2605 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2606 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()
2607 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); in amdgpu_discovery_set_ip_blocks()
2608 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); in amdgpu_discovery_set_ip_blocks()
2609 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); in amdgpu_discovery_set_ip_blocks()
2610 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); in amdgpu_discovery_set_ip_blocks()
2611 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2612 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); in amdgpu_discovery_set_ip_blocks()
2613 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); in amdgpu_discovery_set_ip_blocks()
2614 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); in amdgpu_discovery_set_ip_blocks()
2615 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); in amdgpu_discovery_set_ip_blocks()
2616 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); in amdgpu_discovery_set_ip_blocks()
2620 adev->sdma.num_instances = 5; in amdgpu_discovery_set_ip_blocks()
2621 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()
2622 adev->gmc.num_umc = 4; in amdgpu_discovery_set_ip_blocks()
2623 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); in amdgpu_discovery_set_ip_blocks()
2624 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); in amdgpu_discovery_set_ip_blocks()
2625 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2626 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2627 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2628 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2629 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2630 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2631 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2632 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); in amdgpu_discovery_set_ip_blocks()
2633 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); in amdgpu_discovery_set_ip_blocks()
2634 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); in amdgpu_discovery_set_ip_blocks()
2635 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
2636 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
2637 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
2638 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
2639 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); in amdgpu_discovery_set_ip_blocks()
2640 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); in amdgpu_discovery_set_ip_blocks()
2641 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); in amdgpu_discovery_set_ip_blocks()
2642 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); in amdgpu_discovery_set_ip_blocks()
2647 return -EINVAL; in amdgpu_discovery_set_ip_blocks()
2668 adev->family = AMDGPU_FAMILY_AI; in amdgpu_discovery_set_ip_blocks()
2673 adev->family = AMDGPU_FAMILY_RV; in amdgpu_discovery_set_ip_blocks()
2684 adev->family = AMDGPU_FAMILY_NV; in amdgpu_discovery_set_ip_blocks()
2687 adev->family = AMDGPU_FAMILY_VGH; in amdgpu_discovery_set_ip_blocks()
2688 adev->apu_flags |= AMD_APU_IS_VANGOGH; in amdgpu_discovery_set_ip_blocks()
2691 adev->family = AMDGPU_FAMILY_YC; in amdgpu_discovery_set_ip_blocks()
2694 adev->family = AMDGPU_FAMILY_GC_10_3_6; in amdgpu_discovery_set_ip_blocks()
2697 adev->family = AMDGPU_FAMILY_GC_10_3_7; in amdgpu_discovery_set_ip_blocks()
2702 adev->family = AMDGPU_FAMILY_GC_11_0_0; in amdgpu_discovery_set_ip_blocks()
2706 adev->family = AMDGPU_FAMILY_GC_11_0_1; in amdgpu_discovery_set_ip_blocks()
2711 adev->family = AMDGPU_FAMILY_GC_11_5_0; in amdgpu_discovery_set_ip_blocks()
2715 adev->family = AMDGPU_FAMILY_GC_12_0_0; in amdgpu_discovery_set_ip_blocks()
2718 return -EINVAL; in amdgpu_discovery_set_ip_blocks()
2736 adev->flags |= AMD_IS_APU; in amdgpu_discovery_set_ip_blocks()
2743 adev->gmc.xgmi.supported = true; in amdgpu_discovery_set_ip_blocks()
2747 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0); in amdgpu_discovery_set_ip_blocks()
2753 adev->nbio.funcs = &nbio_v6_1_funcs; in amdgpu_discovery_set_ip_blocks()
2754 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2759 adev->nbio.funcs = &nbio_v7_0_funcs; in amdgpu_discovery_set_ip_blocks()
2760 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2765 adev->nbio.funcs = &nbio_v7_4_funcs; in amdgpu_discovery_set_ip_blocks()
2766 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2769 adev->nbio.funcs = &nbio_v7_9_funcs; in amdgpu_discovery_set_ip_blocks()
2770 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2775 adev->nbio.funcs = &nbio_v7_11_funcs; in amdgpu_discovery_set_ip_blocks()
2776 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2783 adev->nbio.funcs = &nbio_v7_2_funcs; in amdgpu_discovery_set_ip_blocks()
2784 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2794 adev->nbio.funcs = &nbio_v2_3_funcs; in amdgpu_discovery_set_ip_blocks()
2795 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2800 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; in amdgpu_discovery_set_ip_blocks()
2802 adev->nbio.funcs = &nbio_v4_3_funcs; in amdgpu_discovery_set_ip_blocks()
2803 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2807 adev->nbio.funcs = &nbio_v7_7_funcs; in amdgpu_discovery_set_ip_blocks()
2808 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2811 adev->nbio.funcs = &nbif_v6_3_1_funcs; in amdgpu_discovery_set_ip_blocks()
2812 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; in amdgpu_discovery_set_ip_blocks()
2829 adev->hdp.funcs = &hdp_v4_0_funcs; in amdgpu_discovery_set_ip_blocks()
2837 adev->hdp.funcs = &hdp_v5_0_funcs; in amdgpu_discovery_set_ip_blocks()
2840 adev->hdp.funcs = &hdp_v5_2_funcs; in amdgpu_discovery_set_ip_blocks()
2845 adev->hdp.funcs = &hdp_v6_0_funcs; in amdgpu_discovery_set_ip_blocks()
2848 adev->hdp.funcs = &hdp_v7_0_funcs; in amdgpu_discovery_set_ip_blocks()
2858 adev->df.funcs = &df_v3_6_funcs; in amdgpu_discovery_set_ip_blocks()
2865 adev->df.funcs = &df_v1_7_funcs; in amdgpu_discovery_set_ip_blocks()
2868 adev->df.funcs = &df_v4_3_funcs; in amdgpu_discovery_set_ip_blocks()
2871 adev->df.funcs = &df_v4_6_2_funcs; in amdgpu_discovery_set_ip_blocks()
2875 adev->df.funcs = &df_v4_15_funcs; in amdgpu_discovery_set_ip_blocks()
2887 adev->smuio.funcs = &smuio_v9_0_funcs; in amdgpu_discovery_set_ip_blocks()
2895 adev->smuio.funcs = &smuio_v11_0_funcs; in amdgpu_discovery_set_ip_blocks()
2904 adev->smuio.funcs = &smuio_v11_0_6_funcs; in amdgpu_discovery_set_ip_blocks()
2907 adev->smuio.funcs = &smuio_v13_0_funcs; in amdgpu_discovery_set_ip_blocks()
2910 adev->smuio.funcs = &smuio_v13_0_3_funcs; in amdgpu_discovery_set_ip_blocks()
2911 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { in amdgpu_discovery_set_ip_blocks()
2912 adev->flags |= AMD_IS_APU; in amdgpu_discovery_set_ip_blocks()
2919 adev->smuio.funcs = &smuio_v13_0_6_funcs; in amdgpu_discovery_set_ip_blocks()
2922 adev->smuio.funcs = &smuio_v14_0_2_funcs; in amdgpu_discovery_set_ip_blocks()
2933 adev->lsdma.funcs = &lsdma_v6_0_funcs; in amdgpu_discovery_set_ip_blocks()
2937 adev->lsdma.funcs = &lsdma_v7_0_funcs; in amdgpu_discovery_set_ip_blocks()
2951 /* For SR-IOV, PSP needs to be initialized before IH */ in amdgpu_discovery_set_ip_blocks()
2964 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { in amdgpu_discovery_set_ip_blocks()
2971 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { in amdgpu_discovery_set_ip_blocks()
2989 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in amdgpu_discovery_set_ip_blocks()
2991 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { in amdgpu_discovery_set_ip_blocks()