Lines Matching defs:amdgpu_mes
65 struct amdgpu_mes { struct
66 struct amdgpu_device *adev;
68 struct mutex mutex_hidden;
70 struct idr pasid_idr;
71 struct idr gang_id_idr;
72 struct idr queue_id_idr;
73 struct ida doorbell_ida;
75 spinlock_t queue_id_lock;
77 uint32_t sched_version;
78 uint32_t kiq_version;
79 uint32_t fw_version[AMDGPU_MAX_MES_PIPES];
80 bool enable_legacy_queue_map;
82 uint32_t total_max_queue;
83 uint32_t max_doorbell_slices;
85 uint64_t default_process_quantum;
86 uint64_t default_gang_quantum;
88 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES];
89 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES];
91 const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
94 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
95 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
96 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
97 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
100 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
101 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
102 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
103 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
106 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
107 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
109 void *mqd_backup[AMDGPU_MAX_MES_PIPES];
110 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
112 uint32_t vmid_mask_gfxhub;
113 uint32_t vmid_mask_mmhub;
114 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
115 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
116 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
117 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
118 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES];
119 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];
143 const struct amdgpu_mes_funcs *funcs; argument
152 struct amdgpu_mes_process { argument