55 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
94 	uint32_t        hpd;  member
100 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
105 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
110 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
115 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
120 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
125 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
296  * dce_v11_0_hpd_sense - hpd sense callback.
299  * @hpd: hpd (hotplug detect) pin
305 			       enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_sense()  argument
309 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_sense()
312 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v11_0_hpd_sense()
320  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
323  * @hpd: hpd (hotplug detect) pin
325  * Set the polarity of the hpd pin (evergreen+).
328 				      enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_set_polarity()  argument
331 	bool connected = dce_v11_0_hpd_sense(adev, hpd);  in dce_v11_0_hpd_set_polarity()
333 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_set_polarity()
336 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_set_polarity()
341 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_set_polarity()
345  * dce_v11_0_hpd_init - hpd setup callback.
349  * Setup the hpd pins used by the card (evergreen+).
350  * Enable the pin, set the polarity, and enable the hpd interrupts.
363 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_init()
368 			/* don't try to enable hpd on eDP or LVDS avoid breaking the  in dce_v11_0_hpd_init()
373 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
375 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
379 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
381 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
383 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
390 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
392 		dce_v11_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
393 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
394 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
400  * dce_v11_0_hpd_fini - hpd tear down callback.
404  * Tear down the hpd pins used by the card (evergreen+).
405  * Disable the hpd interrupts.
418 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_fini()
421 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_fini()
423 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_fini()
425 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_fini()
2938 	/* HPD hotplug */  in dce_v11_0_sw_init()
3043 	/* initialize hpd */  in dce_v11_0_hw_init()
3203 					unsigned hpd,  in dce_v11_0_set_hpd_irq_state()  argument
3208 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_set_hpd_irq_state()
3209 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_set_hpd_irq_state()
3215 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3217 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3220 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3222 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3356 				  int hpd)  in dce_v11_0_hpd_int_ack()  argument
3360 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_hpd_int_ack()
3361 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_hpd_int_ack()
3365 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_int_ack()
3367 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_int_ack()
3444 	unsigned hpd;  in dce_v11_0_hpd_irq()  local
3451 	hpd = entry->src_data[0];  in dce_v11_0_hpd_irq()
3452 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v11_0_hpd_irq()
3453 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v11_0_hpd_irq()
3456 		dce_v11_0_hpd_int_ack(adev, hpd);  in dce_v11_0_hpd_irq()
3458 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v11_0_hpd_irq()