Lines Matching full:pi
369 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi() local
371 return pi; in kv_get_pi()
451 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt() local
454 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
463 if (pi->caps_db_ramping) { in kv_do_enable_didt()
472 if (pi->caps_td_ramping) { in kv_do_enable_didt()
481 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
493 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt() local
496 if (pi->caps_sq_ramping || in kv_enable_didt()
497 pi->caps_db_ramping || in kv_enable_didt()
498 pi->caps_td_ramping || in kv_enable_didt()
499 pi->caps_tcp_ramping) { in kv_enable_didt()
521 struct kv_power_info *pi = kv_get_pi(adev);
523 if (pi->caps_cac) {
553 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac() local
556 if (pi->caps_cac) { in kv_enable_smc_cac()
560 pi->cac_enabled = false; in kv_enable_smc_cac()
562 pi->cac_enabled = true; in kv_enable_smc_cac()
563 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
565 pi->cac_enabled = false; in kv_enable_smc_cac()
574 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header() local
580 &tmp, pi->sram_end); in kv_process_firmware_header()
583 pi->dpm_table_start = tmp; in kv_process_firmware_header()
587 &tmp, pi->sram_end); in kv_process_firmware_header()
590 pi->soft_regs_start = tmp; in kv_process_firmware_header()
597 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling() local
600 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
603 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
605 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
606 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
613 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval() local
616 pi->graphics_interval = 1; in kv_set_dpm_interval()
619 pi->dpm_table_start + in kv_set_dpm_interval()
621 &pi->graphics_interval, in kv_set_dpm_interval()
622 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
629 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state() local
633 pi->dpm_table_start + in kv_set_dpm_boot_state()
635 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
636 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
654 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value() local
663 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
664 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
678 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage() local
680 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
689 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid() local
691 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
692 pi->graphics_level[index].MinVddNb = in kv_set_vid()
700 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at() local
702 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
710 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable() local
712 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
772 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t() local
776 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
777 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
780 pi->dpm_table_start + in kv_update_sclk_t()
783 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
790 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state() local
796 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
797 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
801 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
805 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
810 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
811 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
815 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
823 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling() local
826 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
829 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
831 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
832 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
839 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings() local
843 pi->dpm_table_start + in kv_upload_dpm_settings()
845 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
847 pi->sram_end); in kv_upload_dpm_settings()
853 pi->dpm_table_start + in kv_upload_dpm_settings()
855 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
856 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
868 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass() local
871 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
893 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table() local
903 pi->uvd_level_count = 0; in kv_populate_uvd_table()
905 if (pi->high_voltage_t && in kv_populate_uvd_table()
906 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
909 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
910 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
911 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
913 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
915 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
922 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
928 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
930 pi->uvd_level_count++; in kv_populate_uvd_table()
934 pi->dpm_table_start + in kv_populate_uvd_table()
936 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
937 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
941 pi->uvd_interval = 1; in kv_populate_uvd_table()
944 pi->dpm_table_start + in kv_populate_uvd_table()
946 &pi->uvd_interval, in kv_populate_uvd_table()
947 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
952 pi->dpm_table_start + in kv_populate_uvd_table()
954 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
956 pi->sram_end); in kv_populate_uvd_table()
964 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table() local
974 pi->vce_level_count = 0; in kv_populate_vce_table()
976 if (pi->high_voltage_t && in kv_populate_vce_table()
977 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
980 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
981 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
983 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
990 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
992 pi->vce_level_count++; in kv_populate_vce_table()
996 pi->dpm_table_start + in kv_populate_vce_table()
998 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
1000 pi->sram_end); in kv_populate_vce_table()
1004 pi->vce_interval = 1; in kv_populate_vce_table()
1007 pi->dpm_table_start + in kv_populate_vce_table()
1009 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
1011 pi->sram_end); in kv_populate_vce_table()
1016 pi->dpm_table_start + in kv_populate_vce_table()
1018 (u8 *)&pi->vce_level, in kv_populate_vce_table()
1020 pi->sram_end); in kv_populate_vce_table()
1027 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table() local
1037 pi->samu_level_count = 0; in kv_populate_samu_table()
1039 if (pi->high_voltage_t && in kv_populate_samu_table()
1040 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
1043 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
1044 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
1046 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
1053 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1055 pi->samu_level_count++; in kv_populate_samu_table()
1059 pi->dpm_table_start + in kv_populate_samu_table()
1061 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
1063 pi->sram_end); in kv_populate_samu_table()
1067 pi->samu_interval = 1; in kv_populate_samu_table()
1070 pi->dpm_table_start + in kv_populate_samu_table()
1072 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
1074 pi->sram_end); in kv_populate_samu_table()
1079 pi->dpm_table_start + in kv_populate_samu_table()
1081 (u8 *)&pi->samu_level, in kv_populate_samu_table()
1083 pi->sram_end); in kv_populate_samu_table()
1093 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table() local
1103 pi->acp_level_count = 0; in kv_populate_acp_table()
1105 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
1106 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
1112 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1114 pi->acp_level_count++; in kv_populate_acp_table()
1118 pi->dpm_table_start + in kv_populate_acp_table()
1120 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
1122 pi->sram_end); in kv_populate_acp_table()
1126 pi->acp_interval = 1; in kv_populate_acp_table()
1129 pi->dpm_table_start + in kv_populate_acp_table()
1131 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
1133 pi->sram_end); in kv_populate_acp_table()
1138 pi->dpm_table_start + in kv_populate_acp_table()
1140 (u8 *)&pi->acp_level, in kv_populate_acp_table()
1142 pi->sram_end); in kv_populate_acp_table()
1151 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings() local
1157 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1158 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1160 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1162 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1164 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1166 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1168 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1170 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1172 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1177 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
1178 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1179 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1181 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1183 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1185 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1187 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1189 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1191 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1193 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1207 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level() local
1209 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
1216 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps() local
1218 pi->current_rps = *rps; in kv_update_current_ps()
1219 pi->current_ps = *new_ps; in kv_update_current_ps()
1220 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
1221 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1228 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps() local
1230 pi->requested_rps = *rps; in kv_update_requested_ps()
1231 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1232 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1233 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1239 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm() local
1242 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1264 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable() local
1310 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1375 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_disable() local
1393 if (pi->caps_vce_pg) /* power on the VCE block */ in kv_dpm_disable()
1395 if (pi->caps_uvd_pg) /* power on the UVD block */ in kv_dpm_disable()
1412 struct kv_power_info *pi = kv_get_pi(adev);
1414 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1415 (u8 *)&value, sizeof(u16), pi->sram_end);
1421 struct kv_power_info *pi = kv_get_pi(adev);
1423 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1424 value, pi->sram_end);
1430 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t() local
1432 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1437 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits() local
1440 if (pi->caps_fps) { in kv_init_fps_limits()
1444 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1446 pi->dpm_table_start + in kv_init_fps_limits()
1448 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1449 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1452 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1455 pi->dpm_table_start + in kv_init_fps_limits()
1457 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1458 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1466 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state() local
1468 pi->uvd_power_gated = false; in kv_init_powergate_state()
1469 pi->vce_power_gated = false; in kv_init_powergate_state()
1470 pi->samu_power_gated = false; in kv_init_powergate_state()
1471 pi->acp_power_gated = false; in kv_init_powergate_state()
1501 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm() local
1509 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1511 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1513 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1514 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1520 pi->dpm_table_start + in kv_update_uvd_dpm()
1522 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1523 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1553 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm() local
1559 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1560 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1562 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1565 pi->dpm_table_start + in kv_update_vce_dpm()
1567 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1569 pi->sram_end); in kv_update_vce_dpm()
1573 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1576 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1587 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm() local
1593 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1594 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1596 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1599 pi->dpm_table_start + in kv_update_samu_dpm()
1601 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1603 pi->sram_end); in kv_update_samu_dpm()
1607 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1610 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1623 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level() local
1626 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1628 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1629 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1632 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1639 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm() local
1645 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1646 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1648 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1651 pi->dpm_table_start + in kv_update_acp_dpm()
1653 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1655 pi->sram_end); in kv_update_acp_dpm()
1659 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1662 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1671 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd() local
1673 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1680 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1684 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1698 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce() local
1700 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1707 if (pi->caps_vce_pg) /* power off the VCE block */ in kv_dpm_powergate_vce()
1710 if (pi->caps_vce_pg) /* power on the VCE block */ in kv_dpm_powergate_vce()
1722 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu() local
1724 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1727 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1731 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1734 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1742 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp() local
1744 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1750 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1754 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1757 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1767 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range() local
1773 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1775 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1776 pi->lowest_valid = i; in kv_set_valid_clock_range()
1781 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1785 pi->highest_valid = i; in kv_set_valid_clock_range()
1787 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1788 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1789 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1790 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1792 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1796 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1798 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1800 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1801 pi->lowest_valid = i; in kv_set_valid_clock_range()
1806 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1811 pi->highest_valid = i; in kv_set_valid_clock_range()
1813 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1815 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1816 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1818 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1820 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1829 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings() local
1833 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1835 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1837 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1839 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1842 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1851 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm() local
1855 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1858 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1861 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1864 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1899 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state() local
1906 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1907 &pi->current_rps); in kv_dpm_pre_set_power_state()
1915 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state() local
1916 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1917 struct amdgpu_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1920 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1929 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1958 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1990 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state() local
1991 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
2006 struct kv_power_info *pi = kv_get_pi(adev);
2021 kv_set_enabled_level(adev, pi->graphics_boot_level);
2029 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table() local
2031 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
2032 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
2034 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
2037 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
2040 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
2087 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state() local
2089 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
2090 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
2091 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
2092 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
2093 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
2094 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
2095 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
2096 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
2142 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock() local
2150 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
2164 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit() local
2171 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2173 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2180 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
2183 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2185 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2201 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules() local
2223 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2253 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2254 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2262 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2265 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2266 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2274 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2280 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2285 pi->battery_state = true; in kv_apply_state_adjust_rules()
2287 pi->battery_state = false; in kv_apply_state_adjust_rules()
2300 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2301 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2302 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2303 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2315 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle() local
2317 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2322 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider() local
2326 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2329 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2330 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2332 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2340 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings() local
2347 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2351 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2352 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2353 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2354 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2357 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2360 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2361 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2364 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2365 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2367 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2368 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2370 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2371 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2372 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2373 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2376 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2377 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2378 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2379 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2382 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2383 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2384 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2385 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2386 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2394 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings() local
2397 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2400 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2401 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2408 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels() local
2416 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2418 if (pi->high_voltage_t && in kv_init_graphics_levels()
2419 (pi->high_voltage_t < in kv_init_graphics_levels()
2425 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2428 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2430 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2434 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2436 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2438 if (pi->high_voltage_t && in kv_init_graphics_levels()
2439 pi->high_voltage_t < in kv_init_graphics_levels()
2445 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2447 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2457 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels() local
2461 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2477 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels() local
2480 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2492 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings() local
2498 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2552 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table() local
2569 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2570 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2571 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2574 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2576 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2578 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2580 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2581 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2586 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2588 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2591 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2593 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2598 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2601 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2605 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2638 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state() local
2641 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2675 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info() local
2687 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2783 struct kv_power_info *pi; in kv_dpm_init() local
2786 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2787 if (pi == NULL) in kv_dpm_init()
2789 adev->pm.dpm.priv = pi; in kv_dpm_init()
2800 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2802 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2804 pi->enable_nb_dpm = true; in kv_dpm_init()
2806 pi->caps_power_containment = true; in kv_dpm_init()
2807 pi->caps_cac = true; in kv_dpm_init()
2808 pi->enable_didt = false; in kv_dpm_init()
2809 if (pi->enable_didt) { in kv_dpm_init()
2810 pi->caps_sq_ramping = true; in kv_dpm_init()
2811 pi->caps_db_ramping = true; in kv_dpm_init()
2812 pi->caps_td_ramping = true; in kv_dpm_init()
2813 pi->caps_tcp_ramping = true; in kv_dpm_init()
2817 pi->caps_sclk_ds = true; in kv_dpm_init()
2819 pi->caps_sclk_ds = false; in kv_dpm_init()
2821 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2822 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2824 pi->bapm_enable = false; in kv_dpm_init()
2826 pi->bapm_enable = true; in kv_dpm_init()
2827 pi->voltage_drop_t = 0; in kv_dpm_init()
2828 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2829 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2830 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2831 pi->caps_uvd_dpm = true; in kv_dpm_init()
2832 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2833 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2834 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2835 pi->caps_stable_p_state = false; in kv_dpm_init()
2848 pi->enable_dpm = true; in kv_dpm_init()
2858 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level() local
2869 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2874 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2875 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2921 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk() local
2922 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2933 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk() local
2935 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()
3261 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_read_sensor() local
3276 pi->graphics_level[pl_index].SclkFrequency); in kv_dpm_read_sensor()