215 		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);  in etnaviv_hw_specs()
216 		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);  in etnaviv_hw_specs()
217 		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);  in etnaviv_hw_specs()
218 		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);  in etnaviv_hw_specs()
362 	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);  in etnaviv_hw_identify()
370 		u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);  in etnaviv_hw_identify()
372 		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);  in etnaviv_hw_identify()
373 		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);  in etnaviv_hw_identify()
374 		gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);  in etnaviv_hw_identify()
381 			gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);  in etnaviv_hw_identify()
382 			gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);  in etnaviv_hw_identify()
398 			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);  in etnaviv_hw_identify()
439 	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);  in etnaviv_hw_identify()
468 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);  in etnaviv_hw_identify()
473 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);  in etnaviv_hw_identify()
475 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);  in etnaviv_hw_identify()
477 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);  in etnaviv_hw_identify()
479 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);  in etnaviv_hw_identify()
481 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);  in etnaviv_hw_identify()
516 		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_gpu_update_clock()
583 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_hw_reset()
592 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_hw_reset()
610 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_hw_reset()
611 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_hw_reset()
766 	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {  in etnaviv_gpu_hw_init()
769 		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;  in etnaviv_gpu_hw_init()
792 		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);  in etnaviv_gpu_hw_init()
801 		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);  in etnaviv_gpu_hw_init()
942 	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
943 	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
946 		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
947 		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
969 	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);  in etnaviv_gpu_debugfs()
970 	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);  in etnaviv_gpu_debugfs()
971 	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);  in etnaviv_gpu_debugfs()
972 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_debugfs()
1082 		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);  in etnaviv_gpu_debugfs()
1083 		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);  in etnaviv_gpu_debugfs()
1084 		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);  in etnaviv_gpu_debugfs()
1464 	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in sync_point_worker()
1536 	status = gpu_read(gpu, status_reg);  in dump_mmu_fault()
1558 				    i, reason, gpu_read(gpu, address_reg));  in dump_mmu_fault()
1567 	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);  in irq_handler()
1678 		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_wait_idle()
1983 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;  in etnaviv_gpu_rpm_suspend()