18 	u32 (*sample)(struct etnaviv_gpu *gpu,
40 static u32 perf_reg_read(struct etnaviv_gpu *gpu,  in perf_reg_read()  argument
44 	gpu_write(gpu, domain->profile_config, signal->data);  in perf_reg_read()
46 	return gpu_read(gpu, domain->profile_read);  in perf_reg_read()
49 static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe)  in pipe_select()  argument
54 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);  in pipe_select()
57 static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu,  in pipe_perf_reg_read()  argument
61 	u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in pipe_perf_reg_read()
65 	lockdep_assert_held(&gpu->lock);  in pipe_perf_reg_read()
67 	for (i = 0; i < gpu->identity.pixel_pipes; i++) {  in pipe_perf_reg_read()
68 		pipe_select(gpu, clock, i);  in pipe_perf_reg_read()
69 		value += perf_reg_read(gpu, domain, signal);  in pipe_perf_reg_read()
72 	/* switch back to pixel pipe 0 to prevent GPU hang */  in pipe_perf_reg_read()
73 	pipe_select(gpu, clock, 0);  in pipe_perf_reg_read()
78 static u32 pipe_reg_read(struct etnaviv_gpu *gpu,  in pipe_reg_read()  argument
82 	u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in pipe_reg_read()
86 	lockdep_assert_held(&gpu->lock);  in pipe_reg_read()
88 	for (i = 0; i < gpu->identity.pixel_pipes; i++) {  in pipe_reg_read()
89 		pipe_select(gpu, clock, i);  in pipe_reg_read()
90 		value += gpu_read(gpu, signal->data);  in pipe_reg_read()
93 	/* switch back to pixel pipe 0 to prevent GPU hang */  in pipe_reg_read()
94 	pipe_select(gpu, clock, 0);  in pipe_reg_read()
99 static u32 hi_total_cycle_read(struct etnaviv_gpu *gpu,  in hi_total_cycle_read()  argument
105 	if (gpu->identity.model == chipModel_GC880 ||  in hi_total_cycle_read()
106 		gpu->identity.model == chipModel_GC2000 ||  in hi_total_cycle_read()
107 		gpu->identity.model == chipModel_GC2100)  in hi_total_cycle_read()
110 	return gpu_read(gpu, reg);  in hi_total_cycle_read()
113 static u32 hi_total_idle_cycle_read(struct etnaviv_gpu *gpu,  in hi_total_idle_cycle_read()  argument
119 	if (gpu->identity.model == chipModel_GC880 ||  in hi_total_idle_cycle_read()
120 		gpu->identity.model == chipModel_GC2000 ||  in hi_total_idle_cycle_read()
121 		gpu->identity.model == chipModel_GC2100)  in hi_total_idle_cycle_read()
124 	return gpu_read(gpu, reg);  in hi_total_idle_cycle_read()
466 static unsigned int num_pm_domains(const struct etnaviv_gpu *gpu)  in num_pm_domains()  argument
473 		if (gpu->identity.features & meta->feature)  in num_pm_domains()
480 static const struct etnaviv_pm_domain *pm_domain(const struct etnaviv_gpu *gpu,  in pm_domain()  argument
489 		if (!(gpu->identity.features & meta->feature))  in pm_domain()
503 int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,  in etnaviv_pm_query_dom()  argument
506 	const unsigned int nr_domains = num_pm_domains(gpu);  in etnaviv_pm_query_dom()
512 	dom = pm_domain(gpu, domain->iter);  in etnaviv_pm_query_dom()
527 int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,  in etnaviv_pm_query_sig()  argument
530 	const unsigned int nr_domains = num_pm_domains(gpu);  in etnaviv_pm_query_sig()
537 	dom = pm_domain(gpu, signal->domain);  in etnaviv_pm_query_sig()
573 void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,  in etnaviv_perfmon_process()  argument
584 	val = sig->sample(gpu, dom, sig);  in etnaviv_perfmon_process()