11 static void hibmc_dp_set_tu(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)  in hibmc_dp_set_tu()  argument
20 	lane_num = dp->link.cap.lanes;  in hibmc_dp_set_tu()
22 		drm_err(dp->dev, "set tu failed, lane num cannot be 0!\n");  in hibmc_dp_set_tu()
27 	rate_ks = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL;  in hibmc_dp_set_tu()
38 	drm_dbg_dp(dp->dev, "tu value: %u.%u value: %u\n",  in hibmc_dp_set_tu()
41 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_PACKET,  in hibmc_dp_set_tu()
43 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_PACKET,  in hibmc_dp_set_tu()
47 static void hibmc_dp_set_sst(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)  in hibmc_dp_set_sst()  argument
55 	fclk = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL;  in hibmc_dp_set_sst()
67 	drm_dbg_dp(dp->dev, "h_active %u v_active %u htotal_size %u hblank_size %u",  in hibmc_dp_set_sst()
69 	drm_dbg_dp(dp->dev, "flink_clock %u pixel_clock %d", fclk, mode->clock / 1000);  in hibmc_dp_set_sst()
71 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_HORIZONTAL_SIZE,  in hibmc_dp_set_sst()
73 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_HORIZONTAL_SIZE,  in hibmc_dp_set_sst()
77 static void hibmc_dp_link_cfg(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)  in hibmc_dp_link_cfg()  argument
89 	hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG0,  in hibmc_dp_link_cfg()
91 	hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG0,  in hibmc_dp_link_cfg()
94 	hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG2,  in hibmc_dp_link_cfg()
96 	hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG2,  in hibmc_dp_link_cfg()
98 	hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG3,  in hibmc_dp_link_cfg()
102 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG0,  in hibmc_dp_link_cfg()
104 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG0,  in hibmc_dp_link_cfg()
106 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG2,  in hibmc_dp_link_cfg()
110 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG1,  in hibmc_dp_link_cfg()
112 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG1,  in hibmc_dp_link_cfg()
114 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG3,  in hibmc_dp_link_cfg()
117 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG3,  in hibmc_dp_link_cfg()
121 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_MSA0,  in hibmc_dp_link_cfg()
123 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_MSA0,  in hibmc_dp_link_cfg()
126 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_VSYNC_POLARITY,  in hibmc_dp_link_cfg()
128 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_HSYNC_POLARITY,  in hibmc_dp_link_cfg()
132 	writel(HIBMC_DP_MSA1, dp->base + HIBMC_DP_VIDEO_MSA1);  in hibmc_dp_link_cfg()
133 	writel(HIBMC_DP_MSA2, dp->base + HIBMC_DP_VIDEO_MSA2);  in hibmc_dp_link_cfg()
135 	hibmc_dp_set_tu(dp, mode);  in hibmc_dp_link_cfg()
137 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_RGB_ENABLE, 0x1);  in hibmc_dp_link_cfg()
138 	hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_VIDEO_MAPPING, 0);  in hibmc_dp_link_cfg()
144 	hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_MODEL_CTRL,  in hibmc_dp_link_cfg()
147 	hibmc_dp_set_sst(dp, mode);  in hibmc_dp_link_cfg()
150 int hibmc_dp_hw_init(struct hibmc_dp *dp)  in hibmc_dp_hw_init()  argument
152 	struct drm_device *drm_dev = dp->drm_dev;  in hibmc_dp_hw_init()
161 	dp->dp_dev = dp_dev;  in hibmc_dp_hw_init()
164 	dp_dev->base = dp->mmio + HIBMC_DP_OFFSET;  in hibmc_dp_hw_init()
184 void hibmc_dp_display_en(struct hibmc_dp *dp, bool enable)  in hibmc_dp_display_en()  argument
186 	struct hibmc_dp_dev *dp_dev = dp->dp_dev;  in hibmc_dp_display_en()
203 int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode)  in hibmc_dp_mode_set()  argument
205 	struct hibmc_dp_dev *dp_dev = dp->dp_dev;  in hibmc_dp_mode_set()
211 			drm_err(dp->drm_dev, "dp link training failed, ret: %d\n", ret);  in hibmc_dp_mode_set()
216 	hibmc_dp_display_en(dp, false);  in hibmc_dp_mode_set()