21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
87  * The higher the value, the lower the dithering depth.
100 #define NS2501_REG1C 0x1c /* low-part of the second register */
101 #define NS2501_REG1D 0x1d /* high-part of the second register */
106  * 2^16/control-value. The low-byte comes first.
108 #define NS2501_REG10 0x10 /* low-byte vertical scaler */
109 #define NS2501_REG11 0x11 /* high-byte vertical scaler */
110 #define NS2501_REGB8 0xb8 /* low-byte horizontal scaler */
111 #define NS2501_REGB9 0xb9 /* high-byte horizontal scaler */
115  * per dimension. One register pair defines the start of the
120 #define NS2501_REGC1 0xc1 /* low-byte horizontal display start */
121 #define NS2501_REGC2 0xc2 /* high-byte horizontal display start */
122 #define NS2501_REGC3 0xc3 /* low-byte horizontal display stop */
123 #define NS2501_REGC4 0xc4 /* high-byte horizontal display stop */
124 #define NS2501_REGC5 0xc5 /* low-byte vertical display start */
125 #define NS2501_REGC6 0xc6 /* high-byte vertical display start */
126 #define NS2501_REGC7 0xc7 /* low-byte vertical display stop */
127 #define NS2501_REGC8 0xc8 /* high-byte vertical display stop */
130  * The following register pair seems to define the start of
132  * register value defines a sync pulse that is later than the
133  * incoming sync, then the register value is ignored and the
136 #define NS2501_REG80 0x80 /* low-byte vsync-start */
137 #define NS2501_REG81 0x81 /* high-byte vsync-start */
142  * This is again a low-high register pair.
148  * The following registers define the end of the front-porch
152 #define NS2501_REG98 0x98 /* horizontal start of display + 256, low */
153 #define NS2501_REG99 0x99 /* horizontal start of display + 256, high */
154 #define NS2501_REG8E 0x8e /* vertical start of the display, low byte */
155 #define NS2501_REG8F 0x8f /* vertical start of the display, high byte */
177  * bits control the depth of the dither. The higher the value,
178  * the LOWER the dithering amplitude. A good value seems to be
179  * 15 (total register value).
194 	u8 value;  member
200  * This is pretty much guess-work from reverse-engineering, so
210 	u16 hstart;		/* horizontal start, registers C1/C2 */
212 	u16 vstart;		/* vertical start, registers C5/C6 */
214 	u16 vsync;		/* manual vertical sync start, 80/81 */
293  * value does not depend on the BIOS and their meaning
299 	[0] = { .offset = 0x0a, .value = 0x81, },
301 	[1] = { .offset = 0x12, .value = 0x02, },
302 	[2] = { .offset = 0x18, .value = 0x07, },
303 	[3] = { .offset = 0x19, .value = 0x00, },
304 	[4] = { .offset = 0x1a, .value = 0x00, }, /* PLL?, ignored */
306 	[5] = { .offset = 0x1e, .value = 0x02, },
307 	[6] = { .offset = 0x1f, .value = 0x40, },
308 	[7] = { .offset = 0x20, .value = 0x00, },
309 	[8] = { .offset = 0x21, .value = 0x00, },
310 	[9] = { .offset = 0x22, .value = 0x00, },
311 	[10] = { .offset = 0x23, .value = 0x00, },
312 	[11] = { .offset = 0x24, .value = 0x00, },
313 	[12] = { .offset = 0x25, .value = 0x00, },
314 	[13] = { .offset = 0x26, .value = 0x00, },
315 	[14] = { .offset = 0x27, .value = 0x00, },
316 	[15] = { .offset = 0x7e, .value = 0x18, },
317 	/* 80-84 are part of the mode-specific configuration */
318 	[16] = { .offset = 0x84, .value = 0x00, },
319 	[17] = { .offset = 0x85, .value = 0x00, },
320 	[18] = { .offset = 0x86, .value = 0x00, },
321 	[19] = { .offset = 0x87, .value = 0x00, },
322 	[20] = { .offset = 0x88, .value = 0x00, },
323 	[21] = { .offset = 0x89, .value = 0x00, },
324 	[22] = { .offset = 0x8a, .value = 0x00, },
325 	[23] = { .offset = 0x8b, .value = 0x00, },
326 	[24] = { .offset = 0x8c, .value = 0x10, },
327 	[25] = { .offset = 0x8d, .value = 0x02, },
328 	/* 8e,8f are part of the mode-specific configuration */
329 	[26] = { .offset = 0x90, .value = 0xff, },
330 	[27] = { .offset = 0x91, .value = 0x07, },
331 	[28] = { .offset = 0x92, .value = 0xa0, },
332 	[29] = { .offset = 0x93, .value = 0x02, },
333 	[30] = { .offset = 0x94, .value = 0x00, },
334 	[31] = { .offset = 0x95, .value = 0x00, },
335 	[32] = { .offset = 0x96, .value = 0x05, },
336 	[33] = { .offset = 0x97, .value = 0x00, },
337 	/* 98,99 are part of the mode-specific configuration */
338 	[34] = { .offset = 0x9a, .value = 0x88, },
339 	[35] = { .offset = 0x9b, .value = 0x00, },
340 	/* 9c,9d are part of the mode-specific configuration */
341 	[36] = { .offset = 0x9e, .value = 0x25, },
342 	[37] = { .offset = 0x9f, .value = 0x03, },
343 	[38] = { .offset = 0xa0, .value = 0x28, },
344 	[39] = { .offset = 0xa1, .value = 0x01, },
345 	[40] = { .offset = 0xa2, .value = 0x28, },
346 	[41] = { .offset = 0xa3, .value = 0x05, },
348 	[42] = { .offset = 0xa4, .value = 0x84, },
349 	[43] = { .offset = 0xa5, .value = 0x00, },
350 	[44] = { .offset = 0xa6, .value = 0x00, },
351 	[45] = { .offset = 0xa7, .value = 0x00, },
352 	[46] = { .offset = 0xa8, .value = 0x00, },
354 	[47] = { .offset = 0xa9, .value = 0x04, },
355 	[48] = { .offset = 0xaa, .value = 0x70, },
356 	[49] = { .offset = 0xab, .value = 0x4f, },
357 	[50] = { .offset = 0xac, .value = 0x00, },
358 	[51] = { .offset = 0xad, .value = 0x00, },
359 	[52] = { .offset = 0xb6, .value = 0x09, },
360 	[53] = { .offset = 0xb7, .value = 0x03, },
361 	/* b8,b9 are part of the mode-specific configuration */
362 	[54] = { .offset = 0xba, .value = 0x00, },
363 	[55] = { .offset = 0xbb, .value = 0x20, },
364 	[56] = { .offset = 0xf3, .value = 0x90, },
365 	[57] = { .offset = 0xf4, .value = 0x00, },
366 	[58] = { .offset = 0xf7, .value = 0x88, },
367 	/* f8 is mode specific, but the value does not matter */
368 	[59] = { .offset = 0xf8, .value = 0x0a, },
369 	[60] = { .offset = 0xf9, .value = 0x00, }
373 	[0] = { .offset = 0x35, .value = 0xff, },
374 	[1] = { .offset = 0x34, .value = 0x00, },
375 	[2] = { .offset = 0x08, .value = 0x30, },
383 #define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr))
393 	struct ns2501_priv *ns = dvo->dev_priv;  in ns2501_readb()
394 	struct i2c_adapter *adapter = dvo->i2c_bus;  in ns2501_readb()
400 		 .addr = dvo->target_addr,  in ns2501_readb()
406 		 .addr = dvo->target_addr,  in ns2501_readb()
421 	if (!ns->quiet) {  in ns2501_readb()
424 		     adapter->name, dvo->target_addr);  in ns2501_readb()
438 	struct ns2501_priv *ns = dvo->dev_priv;  in ns2501_writeb()
439 	struct i2c_adapter *adapter = dvo->i2c_bus;  in ns2501_writeb()
443 		.addr = dvo->target_addr,  in ns2501_writeb()
456 	if (!ns->quiet) {  in ns2501_writeb()
458 			      addr, adapter->name, dvo->target_addr);  in ns2501_writeb()
481 	dvo->i2c_bus = adapter;  in ns2501_init()
482 	dvo->dev_priv = ns;  in ns2501_init()
483 	ns->quiet = true;  in ns2501_init()
490 			      ch, adapter->name, dvo->target_addr);  in ns2501_init()
499 			      ch, adapter->name, dvo->target_addr);  in ns2501_init()
502 	ns->quiet = false;  in ns2501_init()
530 	     mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);  in ns2501_mode_valid()
538 	if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) ||  in ns2501_mode_valid()
539 	    (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) ||  in ns2501_mode_valid()
540 	    (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) {  in ns2501_mode_valid()
552 	struct ns2501_priv *ns = dvo->dev_priv;  in ns2501_mode_set()
557 	     mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);  in ns2501_mode_set()
562 			"hblank start	: %d\n"  in ns2501_mode_set()
564 			"hsync start	: %d\n"  in ns2501_mode_set()
569 			"vblank start	: %d\n"  in ns2501_mode_set()
571 			"vsync start	: %d\n"  in ns2501_mode_set()
574 			adjusted_mode->crtc_clock,  in ns2501_mode_set()
575 			adjusted_mode->crtc_hdisplay,  in ns2501_mode_set()
576 			adjusted_mode->crtc_hblank_start,  in ns2501_mode_set()
577 			adjusted_mode->crtc_hblank_end,  in ns2501_mode_set()
578 			adjusted_mode->crtc_hsync_start,  in ns2501_mode_set()
579 			adjusted_mode->crtc_hsync_end,  in ns2501_mode_set()
580 			adjusted_mode->crtc_htotal,  in ns2501_mode_set()
581 			adjusted_mode->crtc_hskew,  in ns2501_mode_set()
582 			adjusted_mode->crtc_vdisplay,  in ns2501_mode_set()
583 			adjusted_mode->crtc_vblank_start,  in ns2501_mode_set()
584 			adjusted_mode->crtc_vblank_end,  in ns2501_mode_set()
585 			adjusted_mode->crtc_vsync_start,  in ns2501_mode_set()
586 			adjusted_mode->crtc_vsync_end,  in ns2501_mode_set()
587 			adjusted_mode->crtc_vtotal);  in ns2501_mode_set()
589 	if (mode->hdisplay == 640 && mode->vdisplay == 480)  in ns2501_mode_set()
591 	else if (mode->hdisplay == 800 && mode->vdisplay == 600)  in ns2501_mode_set()
593 	else if (mode->hdisplay == 1024 && mode->vdisplay == 768)  in ns2501_mode_set()
600 		ns2501_writeb(dvo, regs_init[i].offset, regs_init[i].value);  in ns2501_mode_set()
602 	/* Write the mode-agnostic values */  in ns2501_mode_set()
605 				mode_agnostic_values[i].value);  in ns2501_mode_set()
607 	/* Write now the mode-specific configuration */  in ns2501_mode_set()
609 	ns->conf = conf;  in ns2501_mode_set()
611 	ns2501_writeb(dvo, NS2501_REG8, conf->conf);  in ns2501_mode_set()
612 	ns2501_writeb(dvo, NS2501_REG1B, conf->pll_a);  in ns2501_mode_set()
613 	ns2501_writeb(dvo, NS2501_REG1C, conf->pll_b & 0xff);  in ns2501_mode_set()
614 	ns2501_writeb(dvo, NS2501_REG1D, conf->pll_b >> 8);  in ns2501_mode_set()
615 	ns2501_writeb(dvo, NS2501_REGC1, conf->hstart & 0xff);  in ns2501_mode_set()
616 	ns2501_writeb(dvo, NS2501_REGC2, conf->hstart >> 8);  in ns2501_mode_set()
617 	ns2501_writeb(dvo, NS2501_REGC3, conf->hstop & 0xff);  in ns2501_mode_set()
618 	ns2501_writeb(dvo, NS2501_REGC4, conf->hstop >> 8);  in ns2501_mode_set()
619 	ns2501_writeb(dvo, NS2501_REGC5, conf->vstart & 0xff);  in ns2501_mode_set()
620 	ns2501_writeb(dvo, NS2501_REGC6, conf->vstart >> 8);  in ns2501_mode_set()
621 	ns2501_writeb(dvo, NS2501_REGC7, conf->vstop & 0xff);  in ns2501_mode_set()
622 	ns2501_writeb(dvo, NS2501_REGC8, conf->vstop >> 8);  in ns2501_mode_set()
623 	ns2501_writeb(dvo, NS2501_REG80, conf->vsync & 0xff);  in ns2501_mode_set()
624 	ns2501_writeb(dvo, NS2501_REG81, conf->vsync >> 8);  in ns2501_mode_set()
625 	ns2501_writeb(dvo, NS2501_REG82, conf->vtotal & 0xff);  in ns2501_mode_set()
626 	ns2501_writeb(dvo, NS2501_REG83, conf->vtotal >> 8);  in ns2501_mode_set()
627 	ns2501_writeb(dvo, NS2501_REG98, conf->hpos & 0xff);  in ns2501_mode_set()
628 	ns2501_writeb(dvo, NS2501_REG99, conf->hpos >> 8);  in ns2501_mode_set()
629 	ns2501_writeb(dvo, NS2501_REG8E, conf->vpos & 0xff);  in ns2501_mode_set()
630 	ns2501_writeb(dvo, NS2501_REG8F, conf->vpos >> 8);  in ns2501_mode_set()
631 	ns2501_writeb(dvo, NS2501_REG9C, conf->voffs & 0xff);  in ns2501_mode_set()
632 	ns2501_writeb(dvo, NS2501_REG9D, conf->voffs >> 8);  in ns2501_mode_set()
633 	ns2501_writeb(dvo, NS2501_REGB8, conf->hscale & 0xff);  in ns2501_mode_set()
634 	ns2501_writeb(dvo, NS2501_REGB9, conf->hscale >> 8);  in ns2501_mode_set()
635 	ns2501_writeb(dvo, NS2501_REG10, conf->vscale & 0xff);  in ns2501_mode_set()
636 	ns2501_writeb(dvo, NS2501_REG11, conf->vscale >> 8);  in ns2501_mode_set()
637 	ns2501_writeb(dvo, NS2501_REGF9, conf->dither);  in ns2501_mode_set()
638 	ns2501_writeb(dvo, NS2501_REG41, conf->syncb);  in ns2501_mode_set()
639 	ns2501_writeb(dvo, NS2501_REGC0, conf->sync);  in ns2501_mode_set()
656 	struct ns2501_priv *ns = dvo->dev_priv;  in ns2501_dpms()
661 		ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync | 0x08);  in ns2501_dpms()
663 		ns2501_writeb(dvo, NS2501_REG41, ns->conf->syncb);  in ns2501_dpms()
669 				ns->conf->conf | NS2501_8_BPAS);  in ns2501_dpms()
670 		if (!(ns->conf->conf & NS2501_8_BPAS))  in ns2501_dpms()
671 			ns2501_writeb(dvo, NS2501_REG8, ns->conf->conf);  in ns2501_dpms()
677 		ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync);  in ns2501_dpms()
692 	struct ns2501_priv *ns = dvo->dev_priv;  in ns2501_destroy()
696 		dvo->dev_priv = NULL;  in ns2501_destroy()