124 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;  in intel_dp_prepare()
174 	bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;  in assert_dp_port()
318 	ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,  in intel_dp_get_hw_state()
356 	tmp = intel_de_read(display, intel_dp->output_reg);  in intel_dp_get_config()
429 			(intel_de_read(display, intel_dp->output_reg) &  in intel_dp_link_down()
443 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
444 	intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_link_down()
447 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
448 	intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_link_down()
467 		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
468 		intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_link_down()
471 		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
472 		intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_link_down()
497 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in g4x_dp_audio_enable()
516 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in g4x_dp_audio_disable()
624 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in cpt_set_link_train()
625 	intel_de_posting_read(display, intel_dp->output_reg);  in cpt_set_link_train()
652 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in g4x_set_link_train()
653 	intel_de_posting_read(display, intel_dp->output_reg);  in g4x_set_link_train()
674 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_enable_port()
675 	intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_enable_port()
686 	u32 dp_reg = intel_de_read(display, intel_dp->output_reg);  in intel_enable_dp()
1048 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in g4x_set_signal_levels()
1049 	intel_de_posting_read(display, intel_dp->output_reg);  in g4x_set_signal_levels()
1096 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in snb_cpu_edp_set_signal_levels()
1097 	intel_de_posting_read(display, intel_dp->output_reg);  in snb_cpu_edp_set_signal_levels()
1148 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in ivb_cpu_edp_set_signal_levels()
1149 	intel_de_posting_read(display, intel_dp->output_reg);  in ivb_cpu_edp_set_signal_levels()
1269 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg);  in intel_dp_encoder_reset()
1286 		 i915_reg_t output_reg, enum port port)  in g4x_dp_init()  argument
1387 	dig_port->dp.output_reg = output_reg;  in g4x_dp_init()