28 #include <drm/display/drm_dsc_helper.h>
56 static int header_credits_available(struct intel_display *display,  in header_credits_available()  argument
59 	return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)  in header_credits_available()
63 static int payload_credits_available(struct intel_display *display,  in payload_credits_available()  argument
66 	return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)  in payload_credits_available()
70 static bool wait_for_header_credits(struct intel_display *display,  in wait_for_header_credits()  argument
73 	if (wait_for_us(header_credits_available(display, dsi_trans) >=  in wait_for_header_credits()
75 		drm_err(display->drm, "DSI header credits not released\n");  in wait_for_header_credits()
82 static bool wait_for_payload_credits(struct intel_display *display,  in wait_for_payload_credits()  argument
85 	if (wait_for_us(payload_credits_available(display, dsi_trans) >=  in wait_for_payload_credits()
87 		drm_err(display->drm, "DSI payload credits not released\n");  in wait_for_payload_credits()
104 	struct intel_display *display = to_intel_display(encoder);  in wait_for_cmds_dispatched_to_panel()  local
114 		wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);  in wait_for_cmds_dispatched_to_panel()
115 		wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);  in wait_for_cmds_dispatched_to_panel()
125 			drm_err(display->drm,  in wait_for_cmds_dispatched_to_panel()
132 		wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);  in wait_for_cmds_dispatched_to_panel()
138 		if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &  in wait_for_cmds_dispatched_to_panel()
140 			drm_err(display->drm, "LPTX bit not cleared\n");  in wait_for_cmds_dispatched_to_panel()
148 	struct intel_display *display = to_intel_display(&intel_dsi->base);  in dsi_send_pkt_payld()  local
156 		drm_err(display->drm, "payload size exceeds max queue limit\n");  in dsi_send_pkt_payld()
163 		if (!wait_for_payload_credits(display, dsi_trans, 1))  in dsi_send_pkt_payld()
169 		intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);  in dsi_send_pkt_payld()
180 	struct intel_display *display = to_intel_display(&intel_dsi->base);  in dsi_send_pkt_hdr()  local
184 	if (!wait_for_header_credits(display, dsi_trans, 1))  in dsi_send_pkt_hdr()
187 	tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));  in dsi_send_pkt_hdr()
206 	intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);  in dsi_send_pkt_hdr()
213 	struct intel_display *display = to_intel_display(crtc_state);  in icl_dsi_frame_update()  local
231 	intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,  in icl_dsi_frame_update()
237 	struct intel_display *display = to_intel_display(encoder);  in dsi_program_swing_and_deemphasis()  local
251 		tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));  in dsi_program_swing_and_deemphasis()
254 		intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);  in dsi_program_swing_and_deemphasis()
255 		intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);  in dsi_program_swing_and_deemphasis()
261 		tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));  in dsi_program_swing_and_deemphasis()
264 		intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);  in dsi_program_swing_and_deemphasis()
265 		intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);  in dsi_program_swing_and_deemphasis()
271 		intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);  in dsi_program_swing_and_deemphasis()
275 			intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),  in dsi_program_swing_and_deemphasis()
283 	struct intel_display *display = to_intel_display(encoder);  in configure_dual_link_mode()  local
289 	if (DISPLAY_VER(display) >= 12) {  in configure_dual_link_mode()
299 	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);  in configure_dual_link_mode()
314 			drm_err(display->drm,  in configure_dual_link_mode()
319 		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,  in configure_dual_link_mode()
326 	intel_de_write(display, dss_ctl1_reg, dss_ctl1);  in configure_dual_link_mode()
347 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_program_esc_clk_div()  local
367 		intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),  in gen11_dsi_program_esc_clk_div()
369 		intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));  in gen11_dsi_program_esc_clk_div()
373 		intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),  in gen11_dsi_program_esc_clk_div()
375 		intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));  in gen11_dsi_program_esc_clk_div()
380 			intel_de_write(display, ADL_MIPIO_DW(port, 8),  in gen11_dsi_program_esc_clk_div()
382 			intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));  in gen11_dsi_program_esc_clk_div()
389 	struct intel_display *display = to_intel_display(&intel_dsi->base);  in get_dsi_io_power_domains()  local
390 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in get_dsi_io_power_domains()
394 		drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);  in get_dsi_io_power_domains()
405 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_enable_io_power()  local
410 		intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),  in gen11_dsi_enable_io_power()
429 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_config_phy_lanes_sequence()  local
438 		intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),  in gen11_dsi_config_phy_lanes_sequence()
441 			intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),  in gen11_dsi_config_phy_lanes_sequence()
447 		intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),  in gen11_dsi_config_phy_lanes_sequence()
449 		tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));  in gen11_dsi_config_phy_lanes_sequence()
452 		intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);  in gen11_dsi_config_phy_lanes_sequence()
456 		    (DISPLAY_VER(display) >= 12)) {  in gen11_dsi_config_phy_lanes_sequence()
457 			intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),  in gen11_dsi_config_phy_lanes_sequence()
460 			tmp = intel_de_read(display,  in gen11_dsi_config_phy_lanes_sequence()
464 			intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),  in gen11_dsi_config_phy_lanes_sequence()
473 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_voltage_swing_program_seq()  local
480 		tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));  in gen11_dsi_voltage_swing_program_seq()
482 		intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);  in gen11_dsi_voltage_swing_program_seq()
483 		intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);  in gen11_dsi_voltage_swing_program_seq()
492 		intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,  in gen11_dsi_voltage_swing_program_seq()
497 		tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));  in gen11_dsi_voltage_swing_program_seq()
499 		intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);  in gen11_dsi_voltage_swing_program_seq()
500 		intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);  in gen11_dsi_voltage_swing_program_seq()
508 		tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));  in gen11_dsi_voltage_swing_program_seq()
510 		intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);  in gen11_dsi_voltage_swing_program_seq()
511 		intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);  in gen11_dsi_voltage_swing_program_seq()
517 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_enable_ddi_buffer()  local
522 		intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);  in gen11_dsi_enable_ddi_buffer()
524 		if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &  in gen11_dsi_enable_ddi_buffer()
527 			drm_err(display->drm, "DDI port:%c buffer idle\n",  in gen11_dsi_enable_ddi_buffer()
536 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_setup_dphy_timings()  local
544 		intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),  in gen11_dsi_setup_dphy_timings()
549 		intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),  in gen11_dsi_setup_dphy_timings()
558 	if (DISPLAY_VER(display) == 11) {  in gen11_dsi_setup_dphy_timings()
561 				intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),  in gen11_dsi_setup_dphy_timings()
569 			intel_de_rmw(display, ICL_DPHY_CHKN(phy),  in gen11_dsi_setup_dphy_timings()
578 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_setup_timings()  local
584 		intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),  in gen11_dsi_setup_timings()
587 	/* shadow register inside display core */  in gen11_dsi_setup_timings()
589 		intel_de_write(display, DSI_CLK_TIMING_PARAM(port),  in gen11_dsi_setup_timings()
592 	/* shadow register inside display core */  in gen11_dsi_setup_timings()
594 		intel_de_write(display, DSI_DATA_TIMING_PARAM(port),  in gen11_dsi_setup_timings()
597 	/* shadow register inside display core */  in gen11_dsi_setup_timings()
598 	if (DISPLAY_VER(display) == 11) {  in gen11_dsi_setup_timings()
601 				intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),  in gen11_dsi_setup_timings()
611 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_gate_clocks()  local
616 	mutex_lock(&display->dpll.lock);  in gen11_dsi_gate_clocks()
617 	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);  in gen11_dsi_gate_clocks()
621 	intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);  in gen11_dsi_gate_clocks()
622 	mutex_unlock(&display->dpll.lock);  in gen11_dsi_gate_clocks()
627 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_ungate_clocks()  local
632 	mutex_lock(&display->dpll.lock);  in gen11_dsi_ungate_clocks()
633 	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);  in gen11_dsi_ungate_clocks()
637 	intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);  in gen11_dsi_ungate_clocks()
638 	mutex_unlock(&display->dpll.lock);  in gen11_dsi_ungate_clocks()
643 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_is_clock_enabled()  local
649 	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);  in gen11_dsi_is_clock_enabled()
662 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_map_pll()  local
668 	mutex_lock(&display->dpll.lock);  in gen11_dsi_map_pll()
670 	val = intel_de_read(display, ICL_DPCLKA_CFGCR0);  in gen11_dsi_map_pll()
675 	intel_de_write(display, ICL_DPCLKA_CFGCR0, val);  in gen11_dsi_map_pll()
680 	intel_de_write(display, ICL_DPCLKA_CFGCR0, val);  in gen11_dsi_map_pll()
682 	intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);  in gen11_dsi_map_pll()
684 	mutex_unlock(&display->dpll.lock);  in gen11_dsi_map_pll()
691 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_configure_transcoder()  local
701 		tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));  in gen11_dsi_configure_transcoder()
757 		if (DISPLAY_VER(display) >= 12) {  in gen11_dsi_configure_transcoder()
790 		intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);  in gen11_dsi_configure_transcoder()
797 			intel_de_rmw(display,  in gen11_dsi_configure_transcoder()
798 				     TRANS_DDI_FUNC_CTL2(display, dsi_trans),  in gen11_dsi_configure_transcoder()
810 		tmp = intel_de_read(display,  in gen11_dsi_configure_transcoder()
811 				    TRANS_DDI_FUNC_CTL(display, dsi_trans));  in gen11_dsi_configure_transcoder()
837 		intel_de_write(display,  in gen11_dsi_configure_transcoder()
838 			       TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);  in gen11_dsi_configure_transcoder()
844 		if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &  in gen11_dsi_configure_transcoder()
846 			drm_err(display->drm, "DSI link not ready\n");  in gen11_dsi_configure_transcoder()
854 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_set_transcoder_timings()  local
921 		drm_err(display->drm, "hactive is less then 256 pixels\n");  in gen11_dsi_set_transcoder_timings()
925 		drm_err(display->drm,  in gen11_dsi_set_transcoder_timings()
931 		intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),  in gen11_dsi_set_transcoder_timings()
940 				drm_err(display->drm,  in gen11_dsi_set_transcoder_timings()
945 			drm_err(display->drm, "hback porch < 16 pixels\n");  in gen11_dsi_set_transcoder_timings()
954 			intel_de_write(display,  in gen11_dsi_set_transcoder_timings()
955 				       TRANS_HSYNC(display, dsi_trans),  in gen11_dsi_set_transcoder_timings()
969 		intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),  in gen11_dsi_set_transcoder_timings()
974 		drm_err(display->drm, "Invalid vsync_end value\n");  in gen11_dsi_set_transcoder_timings()
977 		drm_err(display->drm, "vsync_start less than vactive\n");  in gen11_dsi_set_transcoder_timings()
983 			intel_de_write(display,  in gen11_dsi_set_transcoder_timings()
984 				       TRANS_VSYNC(display, dsi_trans),  in gen11_dsi_set_transcoder_timings()
998 			intel_de_write(display,  in gen11_dsi_set_transcoder_timings()
999 				       TRANS_VSYNCSHIFT(display, dsi_trans),  in gen11_dsi_set_transcoder_timings()
1010 	if (DISPLAY_VER(display) >= 12) {  in gen11_dsi_set_transcoder_timings()
1013 			intel_de_write(display,  in gen11_dsi_set_transcoder_timings()
1014 				       TRANS_VBLANK(display, dsi_trans),  in gen11_dsi_set_transcoder_timings()
1022 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_enable_transcoder()  local
1029 		intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,  in gen11_dsi_enable_transcoder()
1033 		if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),  in gen11_dsi_enable_transcoder()
1035 			drm_err(display->drm,  in gen11_dsi_enable_transcoder()
1043 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_setup_timeouts()  local
1067 		intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),  in gen11_dsi_setup_timeouts()
1074 		intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),  in gen11_dsi_setup_timeouts()
1081 		intel_de_rmw(display, DSI_TA_TO(dsi_trans),  in gen11_dsi_setup_timeouts()
1090 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_config_util_pin()  local
1102 	tmp = intel_de_read(display, UTIL_PIN_CTL);  in gen11_dsi_config_util_pin()
1110 	intel_de_write(display, UTIL_PIN_CTL, tmp);  in gen11_dsi_config_util_pin()
1148 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_powerup_panel()  local
1164 		tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));  in gen11_dsi_powerup_panel()
1171 			drm_err(display->drm,  in gen11_dsi_powerup_panel()
1231 	struct intel_display *display = to_intel_display(encoder);  in icl_apply_kvmr_pipe_a_wa()  local
1233 	if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)  in icl_apply_kvmr_pipe_a_wa()
1234 		intel_de_rmw(display, CHICKEN_PAR1_1,  in icl_apply_kvmr_pipe_a_wa()
1243  * PPI signaling between the Display engine and the DPHY.
1247 	struct intel_display *display = to_intel_display(encoder);  in adlp_set_lp_hs_wakeup_gb()  local
1251 	if (DISPLAY_VER(display) == 13) {  in adlp_set_lp_hs_wakeup_gb()
1253 			intel_de_rmw(display, TGL_DSI_CHKN_REG(port),  in adlp_set_lp_hs_wakeup_gb()
1287 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_disable_transcoder()  local
1296 		intel_de_rmw(display, TRANSCONF(display, dsi_trans),  in gen11_dsi_disable_transcoder()
1300 		if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),  in gen11_dsi_disable_transcoder()
1302 			drm_err(display->drm,  in gen11_dsi_disable_transcoder()
1319 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_deconfigure_trancoder()  local
1328 			intel_de_rmw(display, DSI_CMD_FRMCTL(port),  in gen11_dsi_deconfigure_trancoder()
1335 		tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));  in gen11_dsi_deconfigure_trancoder()
1338 		intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);  in gen11_dsi_deconfigure_trancoder()
1340 		if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &  in gen11_dsi_deconfigure_trancoder()
1343 			drm_err(display->drm, "DSI link not in ULPS\n");  in gen11_dsi_deconfigure_trancoder()
1349 		intel_de_rmw(display,  in gen11_dsi_deconfigure_trancoder()
1350 			     TRANS_DDI_FUNC_CTL(display, dsi_trans),  in gen11_dsi_deconfigure_trancoder()
1358 			intel_de_rmw(display,  in gen11_dsi_deconfigure_trancoder()
1359 				     TRANS_DDI_FUNC_CTL2(display, dsi_trans),  in gen11_dsi_deconfigure_trancoder()
1367 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_disable_port()  local
1373 		intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);  in gen11_dsi_disable_port()
1375 		if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &  in gen11_dsi_disable_port()
1378 			drm_err(display->drm,  in gen11_dsi_disable_port()
1387 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_disable_io_power()  local
1405 		intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),  in gen11_dsi_disable_io_power()
1517 	struct intel_display *display = to_intel_display(&intel_dsi->base);  in gen11_dsi_is_periodic_cmd_mode()  local
1526 	val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));  in gen11_dsi_is_periodic_cmd_mode()
1569 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_sync_state()  local
1580 	if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&  in gen11_dsi_sync_state()
1581 	    !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))  in gen11_dsi_sync_state()
1582 		drm_dbg_kms(display->drm,  in gen11_dsi_sync_state()
1591 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_dsc_compute_config()  local
1593 	int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;  in gen11_dsi_dsc_compute_config()
1620 	drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);  in gen11_dsi_dsc_compute_config()
1621 	drm_WARN_ON(display->drm, vdsc_cfg->simple_422);  in gen11_dsi_dsc_compute_config()
1622 	drm_WARN_ON(display->drm,  in gen11_dsi_dsc_compute_config()
1624 	drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);  in gen11_dsi_dsc_compute_config()
1625 	drm_WARN_ON(display->drm,  in gen11_dsi_dsc_compute_config()
1641 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_compute_config()  local
1675 		drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");  in gen11_dsi_compute_config()
1699 	struct intel_display *display = to_intel_display(encoder);  in gen11_dsi_get_hw_state()  local
1715 		tmp = intel_de_read(display,  in gen11_dsi_get_hw_state()
1716 				    TRANS_DDI_FUNC_CTL(display, dsi_trans));  in gen11_dsi_get_hw_state()
1731 			drm_err(display->drm, "Invalid PIPE input\n");  in gen11_dsi_get_hw_state()
1735 		tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));  in gen11_dsi_get_hw_state()
1845 	struct intel_display *display = to_intel_display(&intel_dsi->base);  in icl_dphy_param_init()  local
1869 		drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n",  in icl_dphy_param_init()
1878 		drm_dbg_kms(display->drm,  in icl_dphy_param_init()
1886 		drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n",  in icl_dphy_param_init()
1894 		drm_dbg_kms(display->drm,  in icl_dphy_param_init()
1903 		drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n",  in icl_dphy_param_init()
1911 		drm_dbg_kms(display->drm,  in icl_dphy_param_init()
1953 void icl_dsi_init(struct intel_display *display,  in icl_dsi_init()  argument
1983 	drm_encoder_init(display->drm, &encoder->base,  in icl_dsi_init()
2009 	drm_connector_init(display->drm, connector,  in icl_dsi_init()
2021 	intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);  in icl_dsi_init()
2023 	mutex_lock(&display->drm->mode_config.mutex);  in icl_dsi_init()
2025 	mutex_unlock(&display->drm->mode_config.mutex);  in icl_dsi_init()
2028 		drm_err(display->drm, "DSI fixed mode info missing\n");  in icl_dsi_init()
2041 	if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))  in icl_dsi_init()
2044 	if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))  in icl_dsi_init()
2058 		drm_dbg_kms(display->drm, "no device found\n");  in icl_dsi_init()