Lines Matching full:phy
56 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
60 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
79 enum phy phy) in icl_set_procmon_ref_values() argument
83 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
85 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
88 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
89 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
93 enum phy phy, i915_reg_t reg, u32 mask, in check_phy_reg() argument
100 "Combo PHY %c reg %08x state mismatch: " in check_phy_reg()
102 phy_name(phy), in check_phy_reg()
111 enum phy phy) in icl_verify_procmon_ref_values() argument
116 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_verify_procmon_ref_values()
118 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), in icl_verify_procmon_ref_values()
120 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), in icl_verify_procmon_ref_values()
122 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), in icl_verify_procmon_ref_values()
128 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) in has_phy_misc() argument
131 * Some platforms only expect PHY_MISC to be programmed for PHY-A and in has_phy_misc()
132 * PHY-B and may not even have instances of the register for the in has_phy_misc()
133 * other combo PHY's. in has_phy_misc()
136 * that we program it for PHY A. in has_phy_misc()
140 return phy == PHY_A; in has_phy_misc()
144 return phy < PHY_C; in has_phy_misc()
150 enum phy phy) in icl_combo_phy_enabled() argument
152 /* The PHY C added by EHL has no PHY_MISC register */ in icl_combo_phy_enabled()
153 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
154 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
156 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
158 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
171 * the PHY. So if combo PHY A is wired up to drive an external in ehl_vbt_ddi_d_present()
185 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); in ehl_vbt_ddi_d_present()
190 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) in phy_is_master() argument
205 * We must set the IREFGEN bit for any PHY acting as a master in phy_is_master()
206 * to another PHY. in phy_is_master()
208 if (phy == PHY_A) in phy_is_master()
211 return phy == PHY_D; in phy_is_master()
213 return phy == PHY_C; in phy_is_master()
219 enum phy phy) in icl_combo_phy_verify_state() argument
224 if (!icl_combo_phy_enabled(dev_priv, phy)) in icl_combo_phy_verify_state()
228 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy), in icl_combo_phy_verify_state()
234 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), in icl_combo_phy_verify_state()
238 ret &= icl_verify_procmon_ref_values(dev_priv, phy); in icl_combo_phy_verify_state()
240 if (phy_is_master(dev_priv, phy)) { in icl_combo_phy_verify_state()
241 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), in icl_combo_phy_verify_state()
248 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), in icl_combo_phy_verify_state()
254 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), in icl_combo_phy_verify_state()
261 enum phy phy, bool is_dsi, in intel_combo_phy_power_up_lanes() argument
305 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), in intel_combo_phy_power_up_lanes()
311 enum phy phy; in icl_combo_phys_init() local
313 for_each_combo_phy(dev_priv, phy) { in icl_combo_phys_init()
317 if (icl_combo_phy_verify_state(dev_priv, phy)) in icl_combo_phys_init()
320 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
323 "Initializing combo PHY %c (Voltage/Process Info : %s)\n", in icl_combo_phys_init()
324 phy_name(phy), procmon->name); in icl_combo_phys_init()
326 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_init()
330 * EHL's combo PHY A can be hooked up to either an external in icl_combo_phys_init()
333 * can't be changed on the fly, so initialize the PHY's mux in icl_combo_phys_init()
337 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
339 phy == PHY_A) { in icl_combo_phys_init()
347 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
351 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
355 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
357 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
360 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
363 icl_set_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
365 if (phy_is_master(dev_priv, phy)) in icl_combo_phys_init()
366 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy), in icl_combo_phys_init()
369 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); in icl_combo_phys_init()
370 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), in icl_combo_phys_init()
377 enum phy phy; in icl_combo_phys_uninit() local
379 for_each_combo_phy_reverse(dev_priv, phy) { in icl_combo_phys_uninit()
380 if (phy == PHY_A && in icl_combo_phys_uninit()
381 !icl_combo_phy_verify_state(dev_priv, phy)) { in icl_combo_phys_uninit()
389 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
390 phy_name(phy)); in icl_combo_phys_uninit()
393 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
394 phy_name(phy)); in icl_combo_phys_uninit()
398 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_uninit()
401 intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0, in icl_combo_phys_uninit()
405 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); in icl_combo_phys_uninit()