157 				  int command, int lane, u32 *val)  in intel_cx0_wait_for_ack()
211 	u32 val;  in __intel_cx0_read_once()  local
283 	u32 val;  in __intel_cx0_write_once()  local
383 	u16 val;  in intel_c20_sram_read()  local
400 	u8 old, val;  in __intel_cx0_rmw()  local
2006 static int intel_c10_phy_check_hdmi_link_rate(int clock)  in intel_c10_phy_check_hdmi_link_rate()
2252 static int intel_c20_phy_check_hdmi_link_rate(int clock)  in intel_c20_phy_check_hdmi_link_rate()
2268 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)  in intel_cx0_phy_check_hdmi_link_rate()
2492 static u8 intel_c20_get_dp_rate(u32 clock)  in intel_c20_get_dp_rate()
2527 static u8 intel_c20_get_hdmi_rate(u32 clock)  in intel_c20_get_hdmi_rate()
2547 static bool is_dp2(u32 clock)  in is_dp2()
2556 static bool is_hdmi_frl(u32 clock)  in is_hdmi_frl()
2579 static int intel_get_c20_custom_width(u32 clock, bool dp)  in intel_get_c20_custom_width()
2596 	u32 clock = crtc_state->port_clock;  in intel_c20_pll_program()  local
2730 	u32 val = 0;  in intel_program_port_clock_ctl()  local
2762 	u32 val = 0;  in intel_cx0_get_powerdown_update()  local
2773 	u32 val = 0;  in intel_cx0_get_powerdown_state()  local
2836 	u32 val = 0;  in intel_cx0_get_pclk_refclk_request()  local
2847 	u32 val = 0;  in intel_cx0_get_pclk_refclk_ack()  local
2962 	u32 val = 0;  in intel_cx0_get_pclk_pll_request()  local
2973 	u32 val = 0;  in intel_cx0_get_pclk_pll_ack()  local
3067 	u32 clock, val;  in intel_mtl_tbt_calc_port_clock()  local
3100 				      int clock)  in intel_mtl_tbt_clock_select()
3134 	u32 val = 0;  in intel_mtl_tbt_pll_enable()  local
3323 	u32 val, clock;  in intel_mtl_port_pll_type()  local
3455 	int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);  in intel_c20pll_state_verify()  local