Lines Matching full:display
201 static bool __intel_display_power_is_enabled(struct intel_display *display, in __intel_display_power_is_enabled() argument
207 if (pm_runtime_suspended(display->drm->dev)) in __intel_display_power_is_enabled()
212 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled()
245 struct intel_display *display = &dev_priv->display; in intel_display_power_is_enabled() local
246 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
250 ret = __intel_display_power_is_enabled(display, domain); in intel_display_power_is_enabled()
257 sanitize_target_dc_state(struct intel_display *display, in sanitize_target_dc_state() argument
260 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
284 * @display: display device
291 void intel_display_power_set_target_dc_state(struct intel_display *display, in intel_display_power_set_target_dc_state() argument
296 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_set_target_dc_state()
299 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); in intel_display_power_set_target_dc_state()
301 if (drm_WARN_ON(display->drm, !power_well)) in intel_display_power_set_target_dc_state()
304 state = sanitize_target_dc_state(display, state); in intel_display_power_set_target_dc_state()
309 dc_off_enabled = intel_power_well_is_enabled(display, power_well); in intel_display_power_set_target_dc_state()
315 intel_power_well_enable(display, power_well); in intel_display_power_set_target_dc_state()
320 intel_power_well_disable(display, power_well); in intel_display_power_set_target_dc_state()
340 struct intel_display *display = container_of(power_domains, in assert_async_put_domain_masks_disjoint() local
344 return !drm_WARN_ON(display->drm, in assert_async_put_domain_masks_disjoint()
353 struct intel_display *display = container_of(power_domains, in __async_put_domains_state_ok() local
362 err |= drm_WARN_ON(display->drm, in __async_put_domains_state_ok()
367 err |= drm_WARN_ON(display->drm, in __async_put_domains_state_ok()
376 struct intel_display *display = container_of(power_domains, in print_power_domains() local
381 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); in print_power_domains()
383 drm_dbg_kms(display->drm, "%s use_count %d\n", in print_power_domains()
391 struct intel_display *display = container_of(power_domains, in print_async_put_domains_state() local
395 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", in print_async_put_domains_state()
456 intel_display_power_grab_async_put_ref(struct intel_display *display, in intel_display_power_grab_async_put_ref() argument
459 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_grab_async_put_ref()
460 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_grab_async_put_ref()
486 __intel_display_power_get_domain(struct intel_display *display, in __intel_display_power_get_domain() argument
489 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_get_domain()
492 if (intel_display_power_grab_async_put_ref(display, domain)) in __intel_display_power_get_domain()
495 for_each_power_domain_well(display, power_well, domain) in __intel_display_power_get_domain()
496 intel_power_well_get(display, power_well); in __intel_display_power_get_domain()
516 struct intel_display *display = &dev_priv->display; in intel_display_power_get() local
517 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get()
521 __intel_display_power_get_domain(display, domain); in intel_display_power_get()
528 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
543 struct intel_display *display = &dev_priv->display; in intel_display_power_get_if_enabled() local
544 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get_if_enabled()
554 if (__intel_display_power_is_enabled(display, domain)) { in intel_display_power_get_if_enabled()
555 __intel_display_power_get_domain(display, domain); in intel_display_power_get_if_enabled()
572 __intel_display_power_put_domain(struct intel_display *display, in __intel_display_power_put_domain() argument
575 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put_domain()
580 drm_WARN(display->drm, !power_domains->domain_use_count[domain], in __intel_display_power_put_domain()
584 drm_WARN(display->drm, in __intel_display_power_put_domain()
591 for_each_power_domain_well_reverse(display, power_well, domain) in __intel_display_power_put_domain()
592 intel_power_well_put(display, power_well); in __intel_display_power_put_domain()
595 static void __intel_display_power_put(struct intel_display *display, in __intel_display_power_put() argument
598 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put()
601 __intel_display_power_put_domain(display, domain); in __intel_display_power_put()
610 struct intel_display *display = container_of(power_domains, in queue_async_put_domains_work() local
613 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); in queue_async_put_domains_work()
615 drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq, in queue_async_put_domains_work()
624 struct intel_display *display = container_of(power_domains, in release_async_put_domains() local
627 struct drm_i915_private *dev_priv = to_i915(display->drm); in release_async_put_domains()
637 __intel_display_power_put_domain(display, domain); in release_async_put_domains()
646 struct intel_display *display = container_of(work, struct intel_display, in intel_display_power_put_async_work() local
648 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_put_async_work()
649 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_put_async_work()
715 struct intel_display *display = &i915->display; in __intel_display_power_put_async() local
716 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put_async()
725 __intel_display_power_put_domain(display, domain); in __intel_display_power_put_async()
730 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); in __intel_display_power_put_async()
756 * intel_display_power_flush_work - flushes the async display power disabling work
769 struct intel_display *display = &i915->display; in intel_display_power_flush_work() local
770 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_flush_work()
794 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
795 * @display: display device instance
801 intel_display_power_flush_work_sync(struct intel_display *display) in intel_display_power_flush_work_sync() argument
803 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_flush_work_sync()
804 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_flush_work_sync()
811 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); in intel_display_power_flush_work_sync()
829 struct intel_display *display = &dev_priv->display; in intel_display_power_put() local
831 __intel_display_power_put(display, domain); in intel_display_power_put()
851 struct intel_display *display = &dev_priv->display; in intel_display_power_put_unchecked() local
853 __intel_display_power_put(display, domain); in intel_display_power_put_unchecked()
863 struct intel_display *display = &i915->display; in intel_display_power_get_in_set() local
866 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); in intel_display_power_get_in_set()
880 struct intel_display *display = &i915->display; in intel_display_power_get_in_set_if_enabled() local
883 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); in intel_display_power_get_in_set_if_enabled()
902 struct intel_display *display = &i915->display; in intel_display_power_put_mask_in_set() local
905 drm_WARN_ON(display->drm, in intel_display_power_put_mask_in_set()
928 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) in get_allowed_dc_mask() argument
934 if (!HAS_DISPLAY(display)) in get_allowed_dc_mask()
937 if (DISPLAY_VER(display) >= 20) in get_allowed_dc_mask()
939 else if (display->platform.dg2) in get_allowed_dc_mask()
941 else if (display->platform.dg1) in get_allowed_dc_mask()
943 else if (DISPLAY_VER(display) >= 12) in get_allowed_dc_mask()
945 else if (display->platform.geminilake || display->platform.broxton) in get_allowed_dc_mask()
947 else if (DISPLAY_VER(display) >= 9) in get_allowed_dc_mask()
957 mask = display->platform.geminilake || display->platform.broxton || in get_allowed_dc_mask()
958 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; in get_allowed_dc_mask()
960 if (!display->params.disable_power_well) in get_allowed_dc_mask()
968 drm_dbg_kms(display->drm, in get_allowed_dc_mask()
973 drm_err(display->drm, in get_allowed_dc_mask()
993 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); in get_allowed_dc_mask()
1000 * @display: display device instance
1005 int intel_power_domains_init(struct intel_display *display) in intel_power_domains_init() argument
1007 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_init()
1009 display->params.disable_power_well = in intel_power_domains_init()
1010 sanitize_disable_power_well_option(display->params.disable_power_well); in intel_power_domains_init()
1012 get_allowed_dc_mask(display, display->params.enable_dc); in intel_power_domains_init()
1015 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6); in intel_power_domains_init()
1027 * @display: display device instance
1031 void intel_power_domains_cleanup(struct intel_display *display) in intel_power_domains_cleanup() argument
1033 intel_display_power_map_cleanup(&display->power.domains); in intel_power_domains_cleanup()
1036 static void intel_power_domains_sync_hw(struct intel_display *display) in intel_power_domains_sync_hw() argument
1038 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_sync_hw()
1042 for_each_power_well(display, power_well) in intel_power_domains_sync_hw()
1043 intel_power_well_sync_hw(display, power_well); in intel_power_domains_sync_hw()
1047 static void gen9_dbuf_slice_set(struct intel_display *display, in gen9_dbuf_slice_set() argument
1053 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, in gen9_dbuf_slice_set()
1055 intel_de_posting_read(display, reg); in gen9_dbuf_slice_set()
1058 state = intel_de_read(display, reg) & DBUF_POWER_STATE; in gen9_dbuf_slice_set()
1059 drm_WARN(display->drm, enable != state, in gen9_dbuf_slice_set()
1067 struct intel_display *display = &dev_priv->display; in gen9_dbuf_slices_update() local
1068 struct i915_power_domains *power_domains = &display->power.domains; in gen9_dbuf_slices_update()
1069 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; in gen9_dbuf_slices_update()
1072 drm_WARN(display->drm, req_slices & ~slice_mask, in gen9_dbuf_slices_update()
1076 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", in gen9_dbuf_slices_update()
1088 for_each_dbuf_slice(display, slice) in gen9_dbuf_slices_update()
1089 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice)); in gen9_dbuf_slices_update()
1091 display->dbuf.enabled_slices = req_slices; in gen9_dbuf_slices_update()
1096 static void gen9_dbuf_enable(struct intel_display *display) in gen9_dbuf_enable() argument
1098 struct drm_i915_private *dev_priv = to_i915(display->drm); in gen9_dbuf_enable()
1101 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); in gen9_dbuf_enable()
1103 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; in gen9_dbuf_enable()
1105 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_enable()
1106 intel_pmdemand_program_dbuf(display, slices_mask); in gen9_dbuf_enable()
1115 static void gen9_dbuf_disable(struct intel_display *display) in gen9_dbuf_disable() argument
1117 struct drm_i915_private *dev_priv = to_i915(display->drm); in gen9_dbuf_disable()
1121 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_disable()
1122 intel_pmdemand_program_dbuf(display, 0); in gen9_dbuf_disable()
1125 static void gen12_dbuf_slices_config(struct intel_display *display) in gen12_dbuf_slices_config() argument
1129 if (display->platform.alderlake_p) in gen12_dbuf_slices_config()
1132 for_each_dbuf_slice(display, slice) in gen12_dbuf_slices_config()
1133 intel_de_rmw(display, DBUF_CTL_S(slice), in gen12_dbuf_slices_config()
1138 static void icl_mbus_init(struct intel_display *display) in icl_mbus_init() argument
1140 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; in icl_mbus_init()
1143 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) in icl_mbus_init()
1160 if (DISPLAY_VER(display) == 12) in icl_mbus_init()
1164 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); in icl_mbus_init()
1167 static void hsw_assert_cdclk(struct intel_display *display) in hsw_assert_cdclk() argument
1169 u32 val = intel_de_read(display, LCPLL_CTL); in hsw_assert_cdclk()
1178 drm_err(display->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1181 drm_err(display->drm, "LCPLL is disabled\n"); in hsw_assert_cdclk()
1184 drm_err(display->drm, "LCPLL not using non-SSC reference\n"); in hsw_assert_cdclk()
1187 static void assert_can_disable_lcpll(struct intel_display *display) in assert_can_disable_lcpll() argument
1189 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_can_disable_lcpll()
1192 for_each_intel_crtc(display->drm, crtc) in assert_can_disable_lcpll()
1193 INTEL_DISPLAY_STATE_WARN(display, crtc->active, in assert_can_disable_lcpll()
1197 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2), in assert_can_disable_lcpll()
1198 "Display power well on\n"); in assert_can_disable_lcpll()
1199 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1200 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1202 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1203 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1205 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1206 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1208 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1209 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, in assert_can_disable_lcpll()
1211 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1212 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1214 if (display->platform.haswell) in assert_can_disable_lcpll()
1215 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1216 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1218 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1219 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, in assert_can_disable_lcpll()
1221 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1222 …(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABL… in assert_can_disable_lcpll()
1224 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1225 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE, in assert_can_disable_lcpll()
1234 INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv), in assert_can_disable_lcpll()
1238 static u32 hsw_read_dcomp(struct intel_display *display) in hsw_read_dcomp() argument
1240 if (display->platform.haswell) in hsw_read_dcomp()
1241 return intel_de_read(display, D_COMP_HSW); in hsw_read_dcomp()
1243 return intel_de_read(display, D_COMP_BDW); in hsw_read_dcomp()
1246 static void hsw_write_dcomp(struct intel_display *display, u32 val) in hsw_write_dcomp() argument
1248 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_write_dcomp()
1250 if (display->platform.haswell) { in hsw_write_dcomp()
1252 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); in hsw_write_dcomp()
1254 intel_de_write(display, D_COMP_BDW, val); in hsw_write_dcomp()
1255 intel_de_posting_read(display, D_COMP_BDW); in hsw_write_dcomp()
1261 * - Sequence for display software to disable LCPLL
1262 * - Sequence for display software to allow package C8+
1264 * register. Callers should take care of disabling all the display engine
1267 static void hsw_disable_lcpll(struct intel_display *display, in hsw_disable_lcpll() argument
1272 assert_can_disable_lcpll(display); in hsw_disable_lcpll()
1274 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1278 intel_de_write(display, LCPLL_CTL, val); in hsw_disable_lcpll()
1280 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & in hsw_disable_lcpll()
1282 drm_err(display->drm, "Switching to FCLK failed\n"); in hsw_disable_lcpll()
1284 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1288 intel_de_write(display, LCPLL_CTL, val); in hsw_disable_lcpll()
1289 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1291 if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) in hsw_disable_lcpll()
1292 drm_err(display->drm, "LCPLL still locked\n"); in hsw_disable_lcpll()
1294 val = hsw_read_dcomp(display); in hsw_disable_lcpll()
1296 hsw_write_dcomp(display, val); in hsw_disable_lcpll()
1299 if (wait_for((hsw_read_dcomp(display) & in hsw_disable_lcpll()
1301 drm_err(display->drm, "D_COMP RCOMP still in progress\n"); in hsw_disable_lcpll()
1304 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); in hsw_disable_lcpll()
1305 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1313 static void hsw_restore_lcpll(struct intel_display *display) in hsw_restore_lcpll() argument
1315 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); in hsw_restore_lcpll()
1318 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1332 intel_de_write(display, LCPLL_CTL, val); in hsw_restore_lcpll()
1333 intel_de_posting_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1336 val = hsw_read_dcomp(display); in hsw_restore_lcpll()
1339 hsw_write_dcomp(display, val); in hsw_restore_lcpll()
1341 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1343 intel_de_write(display, LCPLL_CTL, val); in hsw_restore_lcpll()
1345 if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) in hsw_restore_lcpll()
1346 drm_err(display->drm, "LCPLL not locked yet\n"); in hsw_restore_lcpll()
1349 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); in hsw_restore_lcpll()
1351 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & in hsw_restore_lcpll()
1353 drm_err(display->drm, in hsw_restore_lcpll()
1359 intel_update_cdclk(display); in hsw_restore_lcpll()
1360 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
1383 * For more, read "Display Sequences for Package C8" on the hardware
1386 static void hsw_enable_pc8(struct intel_display *display) in hsw_enable_pc8() argument
1388 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_enable_pc8()
1390 drm_dbg_kms(display->drm, "Enabling package C8+\n"); in hsw_enable_pc8()
1393 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in hsw_enable_pc8()
1397 hsw_disable_lcpll(display, true, true); in hsw_enable_pc8()
1400 static void hsw_disable_pc8(struct intel_display *display) in hsw_disable_pc8() argument
1402 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_disable_pc8()
1404 drm_dbg_kms(display->drm, "Disabling package C8+\n"); in hsw_disable_pc8()
1406 hsw_restore_lcpll(display); in hsw_disable_pc8()
1409 /* Many display registers don't survive PC8+ */ in hsw_disable_pc8()
1415 static void intel_pch_reset_handshake(struct intel_display *display, in intel_pch_reset_handshake() argument
1421 if (display->platform.ivybridge) { in intel_pch_reset_handshake()
1429 if (DISPLAY_VER(display) >= 14) in intel_pch_reset_handshake()
1432 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0); in intel_pch_reset_handshake()
1435 static void skl_display_core_init(struct intel_display *display, in skl_display_core_init() argument
1438 struct drm_i915_private *dev_priv = to_i915(display->drm); in skl_display_core_init()
1439 struct i915_power_domains *power_domains = &display->power.domains; in skl_display_core_init()
1442 gen9_set_dc_state(display, DC_STATE_DISABLE); in skl_display_core_init()
1445 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); in skl_display_core_init()
1447 if (!HAS_DISPLAY(display)) in skl_display_core_init()
1453 well = lookup_power_well(display, SKL_DISP_PW_1); in skl_display_core_init()
1454 intel_power_well_enable(display, well); in skl_display_core_init()
1456 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO); in skl_display_core_init()
1457 intel_power_well_enable(display, well); in skl_display_core_init()
1461 intel_cdclk_init_hw(display); in skl_display_core_init()
1463 gen9_dbuf_enable(display); in skl_display_core_init()
1466 intel_dmc_load_program(display); in skl_display_core_init()
1469 static void skl_display_core_uninit(struct intel_display *display) in skl_display_core_uninit() argument
1471 struct i915_power_domains *power_domains = &display->power.domains; in skl_display_core_uninit()
1474 if (!HAS_DISPLAY(display)) in skl_display_core_uninit()
1477 gen9_disable_dc_states(display); in skl_display_core_uninit()
1480 gen9_dbuf_disable(display); in skl_display_core_uninit()
1482 intel_cdclk_uninit_hw(display); in skl_display_core_uninit()
1495 well = lookup_power_well(display, SKL_DISP_PW_1); in skl_display_core_uninit()
1496 intel_power_well_disable(display, well); in skl_display_core_uninit()
1503 static void bxt_display_core_init(struct intel_display *display, bool resume) in bxt_display_core_init() argument
1505 struct i915_power_domains *power_domains = &display->power.domains; in bxt_display_core_init()
1508 gen9_set_dc_state(display, DC_STATE_DISABLE); in bxt_display_core_init()
1516 intel_pch_reset_handshake(display, false); in bxt_display_core_init()
1518 if (!HAS_DISPLAY(display)) in bxt_display_core_init()
1524 well = lookup_power_well(display, SKL_DISP_PW_1); in bxt_display_core_init()
1525 intel_power_well_enable(display, well); in bxt_display_core_init()
1529 intel_cdclk_init_hw(display); in bxt_display_core_init()
1531 gen9_dbuf_enable(display); in bxt_display_core_init()
1534 intel_dmc_load_program(display); in bxt_display_core_init()
1537 static void bxt_display_core_uninit(struct intel_display *display) in bxt_display_core_uninit() argument
1539 struct i915_power_domains *power_domains = &display->power.domains; in bxt_display_core_uninit()
1542 if (!HAS_DISPLAY(display)) in bxt_display_core_uninit()
1545 gen9_disable_dc_states(display); in bxt_display_core_uninit()
1548 gen9_dbuf_disable(display); in bxt_display_core_uninit()
1550 intel_cdclk_uninit_hw(display); in bxt_display_core_uninit()
1561 well = lookup_power_well(display, SKL_DISP_PW_1); in bxt_display_core_uninit()
1562 intel_power_well_disable(display, well); in bxt_display_core_uninit()
1599 static void tgl_bw_buddy_init(struct intel_display *display) in tgl_bw_buddy_init() argument
1601 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_bw_buddy_init()
1605 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; in tgl_bw_buddy_init()
1609 if (display->platform.dgfx && !display->platform.dg1) in tgl_bw_buddy_init()
1612 if (display->platform.alderlake_s || in tgl_bw_buddy_init()
1613 (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))) in tgl_bw_buddy_init()
1625 drm_dbg_kms(display->drm, in tgl_bw_buddy_init()
1628 intel_de_write(display, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1632 intel_de_write(display, BW_BUDDY_PAGE_MASK(i), in tgl_bw_buddy_init()
1636 if (DISPLAY_VER(display) == 12) in tgl_bw_buddy_init()
1637 intel_de_rmw(display, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1644 static void icl_display_core_init(struct intel_display *display, in icl_display_core_init() argument
1647 struct drm_i915_private *dev_priv = to_i915(display->drm); in icl_display_core_init()
1648 struct i915_power_domains *power_domains = &display->power.domains; in icl_display_core_init()
1651 gen9_set_dc_state(display, DC_STATE_DISABLE); in icl_display_core_init()
1656 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, in icl_display_core_init()
1660 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); in icl_display_core_init()
1662 if (!HAS_DISPLAY(display)) in icl_display_core_init()
1673 well = lookup_power_well(display, SKL_DISP_PW_1); in icl_display_core_init()
1674 intel_power_well_enable(display, well); in icl_display_core_init()
1677 if (DISPLAY_VER(display) == 14) in icl_display_core_init()
1678 intel_de_rmw(display, DC_STATE_EN, in icl_display_core_init()
1682 intel_cdclk_init_hw(display); in icl_display_core_init()
1684 if (DISPLAY_VER(display) >= 12) in icl_display_core_init()
1685 gen12_dbuf_slices_config(display); in icl_display_core_init()
1688 gen9_dbuf_enable(display); in icl_display_core_init()
1691 icl_mbus_init(display); in icl_display_core_init()
1694 if (DISPLAY_VER(display) >= 12) in icl_display_core_init()
1695 tgl_bw_buddy_init(display); in icl_display_core_init()
1698 if (display->platform.dg2) in icl_display_core_init()
1702 if (DISPLAY_VERx100(display) == 1401) in icl_display_core_init()
1703 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); in icl_display_core_init()
1706 intel_dmc_load_program(display); in icl_display_core_init()
1709 if (IS_DISPLAY_VERx100(display, 1200, 1300)) in icl_display_core_init()
1710 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, in icl_display_core_init()
1715 if (DISPLAY_VER(display) == 13) in icl_display_core_init()
1716 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); in icl_display_core_init()
1719 if (DISPLAY_VER(display) == 20) { in icl_display_core_init()
1720 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
1722 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
1727 static void icl_display_core_uninit(struct intel_display *display) in icl_display_core_uninit() argument
1729 struct drm_i915_private *dev_priv = to_i915(display->drm); in icl_display_core_uninit()
1730 struct i915_power_domains *power_domains = &display->power.domains; in icl_display_core_uninit()
1733 if (!HAS_DISPLAY(display)) in icl_display_core_uninit()
1736 gen9_disable_dc_states(display); in icl_display_core_uninit()
1737 intel_dmc_disable_program(display); in icl_display_core_uninit()
1739 /* 1. Disable all display engine functions -> aready done */ in icl_display_core_uninit()
1742 gen9_dbuf_disable(display); in icl_display_core_uninit()
1745 intel_cdclk_uninit_hw(display); in icl_display_core_uninit()
1747 if (DISPLAY_VER(display) == 14) in icl_display_core_uninit()
1748 intel_de_rmw(display, DC_STATE_EN, 0, in icl_display_core_uninit()
1757 well = lookup_power_well(display, SKL_DISP_PW_1); in icl_display_core_uninit()
1758 intel_power_well_disable(display, well); in icl_display_core_uninit()
1765 static void chv_phy_control_init(struct intel_display *display) in chv_phy_control_init() argument
1768 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); in chv_phy_control_init()
1770 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); in chv_phy_control_init()
1779 display->power.chv_phy_control = in chv_phy_control_init()
1793 if (intel_power_well_is_enabled(display, cmn_bc)) { in chv_phy_control_init()
1794 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); in chv_phy_control_init()
1801 display->power.chv_phy_control |= in chv_phy_control_init()
1804 display->power.chv_phy_control |= in chv_phy_control_init()
1811 display->power.chv_phy_control |= in chv_phy_control_init()
1814 display->power.chv_phy_control |= in chv_phy_control_init()
1817 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
1819 display->power.chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
1821 display->power.chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
1824 if (intel_power_well_is_enabled(display, cmn_d)) { in chv_phy_control_init()
1825 u32 status = intel_de_read(display, DPIO_PHY_STATUS); in chv_phy_control_init()
1833 display->power.chv_phy_control |= in chv_phy_control_init()
1836 display->power.chv_phy_control |= in chv_phy_control_init()
1839 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
1841 display->power.chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
1843 display->power.chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
1846 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", in chv_phy_control_init()
1847 display->power.chv_phy_control); in chv_phy_control_init()
1852 static void vlv_cmnlane_wa(struct intel_display *display) in vlv_cmnlane_wa() argument
1855 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); in vlv_cmnlane_wa()
1857 lookup_power_well(display, VLV_DISP_PW_DISP2D); in vlv_cmnlane_wa()
1859 /* If the display might be already active skip this */ in vlv_cmnlane_wa()
1860 if (intel_power_well_is_enabled(display, cmn) && in vlv_cmnlane_wa()
1861 intel_power_well_is_enabled(display, disp2d) && in vlv_cmnlane_wa()
1862 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST) in vlv_cmnlane_wa()
1865 drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); in vlv_cmnlane_wa()
1868 intel_power_well_enable(display, disp2d); in vlv_cmnlane_wa()
1877 intel_power_well_disable(display, cmn); in vlv_cmnlane_wa()
1880 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) in vlv_punit_is_power_gated() argument
1882 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_punit_is_power_gated()
1892 static void assert_ved_power_gated(struct intel_display *display) in assert_ved_power_gated() argument
1894 drm_WARN(display->drm, in assert_ved_power_gated()
1895 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0), in assert_ved_power_gated()
1899 static void assert_isp_power_gated(struct intel_display *display) in assert_isp_power_gated() argument
1907 drm_WARN(display->drm, !pci_dev_present(isp_ids) && in assert_isp_power_gated()
1908 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0), in assert_isp_power_gated()
1912 static void intel_power_domains_verify_state(struct intel_display *display);
1916 * @display: display device instance
1930 void intel_power_domains_init_hw(struct intel_display *display, bool resume) in intel_power_domains_init_hw() argument
1932 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_init_hw()
1933 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_init_hw()
1937 if (DISPLAY_VER(display) >= 11) { in intel_power_domains_init_hw()
1938 icl_display_core_init(display, resume); in intel_power_domains_init_hw()
1939 } else if (display->platform.geminilake || display->platform.broxton) { in intel_power_domains_init_hw()
1940 bxt_display_core_init(display, resume); in intel_power_domains_init_hw()
1941 } else if (DISPLAY_VER(display) == 9) { in intel_power_domains_init_hw()
1942 skl_display_core_init(display, resume); in intel_power_domains_init_hw()
1943 } else if (display->platform.cherryview) { in intel_power_domains_init_hw()
1945 chv_phy_control_init(display); in intel_power_domains_init_hw()
1947 assert_isp_power_gated(display); in intel_power_domains_init_hw()
1948 } else if (display->platform.valleyview) { in intel_power_domains_init_hw()
1950 vlv_cmnlane_wa(display); in intel_power_domains_init_hw()
1952 assert_ved_power_gated(display); in intel_power_domains_init_hw()
1953 assert_isp_power_gated(display); in intel_power_domains_init_hw()
1954 } else if (display->platform.broadwell || display->platform.haswell) { in intel_power_domains_init_hw()
1955 hsw_assert_cdclk(display); in intel_power_domains_init_hw()
1956 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); in intel_power_domains_init_hw()
1957 } else if (display->platform.ivybridge) { in intel_power_domains_init_hw()
1958 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); in intel_power_domains_init_hw()
1963 * initialization and to make sure we keep BIOS enabled display HW in intel_power_domains_init_hw()
1964 * resources powered until display HW readout is complete. We drop in intel_power_domains_init_hw()
1967 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_init_hw()
1972 if (!display->params.disable_power_well) { in intel_power_domains_init_hw()
1973 drm_WARN_ON(display->drm, power_domains->disable_wakeref); in intel_power_domains_init_hw()
1974 display->power.domains.disable_wakeref = intel_display_power_get(i915, in intel_power_domains_init_hw()
1977 intel_power_domains_sync_hw(display); in intel_power_domains_init_hw()
1984 * @display: display device instance
1986 * De-initializes the display power domain HW state. It also ensures that the
1993 void intel_power_domains_driver_remove(struct intel_display *display) in intel_power_domains_driver_remove() argument
1995 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_driver_remove()
1997 fetch_and_zero(&display->power.domains.init_wakeref); in intel_power_domains_driver_remove()
2000 if (!display->params.disable_power_well) in intel_power_domains_driver_remove()
2002 fetch_and_zero(&display->power.domains.disable_wakeref)); in intel_power_domains_driver_remove()
2004 intel_display_power_flush_work_sync(display); in intel_power_domains_driver_remove()
2006 intel_power_domains_verify_state(display); in intel_power_domains_driver_remove()
2014 * @display: display device instance
2017 * The function will disable all display power wells that BIOS has enabled
2022 void intel_power_domains_sanitize_state(struct intel_display *display) in intel_power_domains_sanitize_state() argument
2024 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_sanitize_state()
2029 for_each_power_well_reverse(display, power_well) { in intel_power_domains_sanitize_state()
2031 !intel_power_well_is_enabled(display, power_well)) in intel_power_domains_sanitize_state()
2034 drm_dbg_kms(display->drm, in intel_power_domains_sanitize_state()
2037 intel_power_well_disable(display, power_well); in intel_power_domains_sanitize_state()
2044 * intel_power_domains_enable - enable toggling of display power wells
2045 * @display: display device instance
2047 * Enable the ondemand enabling/disabling of the display power wells. Note that
2049 * only at specific points of the display modeset sequence, thus they are not
2052 * of display HW readout (which will acquire the power references reflecting
2055 void intel_power_domains_enable(struct intel_display *display) in intel_power_domains_enable() argument
2057 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_enable()
2059 fetch_and_zero(&display->power.domains.init_wakeref); in intel_power_domains_enable()
2062 intel_power_domains_verify_state(display); in intel_power_domains_enable()
2066 * intel_power_domains_disable - disable toggling of display power wells
2067 * @display: display device instance
2069 * Disable the ondemand enabling/disabling of the display power wells. See
2072 void intel_power_domains_disable(struct intel_display *display) in intel_power_domains_disable() argument
2074 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_disable()
2075 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_disable()
2077 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_disable()
2081 intel_power_domains_verify_state(display); in intel_power_domains_disable()
2086 * @display: display device instance
2095 void intel_power_domains_suspend(struct intel_display *display, bool s2idle) in intel_power_domains_suspend() argument
2097 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_suspend()
2098 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_suspend()
2112 intel_dmc_has_payload(display)) { in intel_power_domains_suspend()
2114 intel_power_domains_verify_state(display); in intel_power_domains_suspend()
2122 if (!display->params.disable_power_well) in intel_power_domains_suspend()
2124 fetch_and_zero(&display->power.domains.disable_wakeref)); in intel_power_domains_suspend()
2127 intel_power_domains_verify_state(display); in intel_power_domains_suspend()
2129 if (DISPLAY_VER(display) >= 11) in intel_power_domains_suspend()
2130 icl_display_core_uninit(display); in intel_power_domains_suspend()
2131 else if (display->platform.geminilake || display->platform.broxton) in intel_power_domains_suspend()
2132 bxt_display_core_uninit(display); in intel_power_domains_suspend()
2133 else if (DISPLAY_VER(display) == 9) in intel_power_domains_suspend()
2134 skl_display_core_uninit(display); in intel_power_domains_suspend()
2141 * @display: display device instance
2149 void intel_power_domains_resume(struct intel_display *display) in intel_power_domains_resume() argument
2151 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_resume()
2152 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_resume()
2155 intel_power_domains_init_hw(display, true); in intel_power_domains_resume()
2158 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_resume()
2163 intel_power_domains_verify_state(display); in intel_power_domains_resume()
2168 static void intel_power_domains_dump_info(struct intel_display *display) in intel_power_domains_dump_info() argument
2170 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_dump_info()
2173 for_each_power_well(display, power_well) { in intel_power_domains_dump_info()
2176 drm_dbg_kms(display->drm, "%-25s %d\n", in intel_power_domains_dump_info()
2180 drm_dbg_kms(display->drm, " %-23s %d\n", in intel_power_domains_dump_info()
2188 * @display: display device instance
2196 static void intel_power_domains_verify_state(struct intel_display *display) in intel_power_domains_verify_state() argument
2198 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_verify_state()
2207 for_each_power_well(display, power_well) { in intel_power_domains_verify_state()
2212 enabled = intel_power_well_is_enabled(display, power_well); in intel_power_domains_verify_state()
2216 drm_err(display->drm, in intel_power_domains_verify_state()
2226 drm_err(display->drm, in intel_power_domains_verify_state()
2240 intel_power_domains_dump_info(display); in intel_power_domains_verify_state()
2250 static void intel_power_domains_verify_state(struct intel_display *display) in intel_power_domains_verify_state() argument
2256 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) in intel_display_power_suspend_late() argument
2258 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_suspend_late()
2260 intel_power_domains_suspend(display, s2idle); in intel_display_power_suspend_late()
2262 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_suspend_late()
2263 display->platform.broxton) { in intel_display_power_suspend_late()
2264 bxt_enable_dc9(display); in intel_display_power_suspend_late()
2265 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_suspend_late()
2266 hsw_enable_pc8(display); in intel_display_power_suspend_late()
2274 void intel_display_power_resume_early(struct intel_display *display) in intel_display_power_resume_early() argument
2276 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_resume_early()
2278 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_resume_early()
2279 display->platform.broxton) { in intel_display_power_resume_early()
2280 gen9_sanitize_dc_state(display); in intel_display_power_resume_early()
2281 bxt_disable_dc9(display); in intel_display_power_resume_early()
2282 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_resume_early()
2283 hsw_disable_pc8(display); in intel_display_power_resume_early()
2290 intel_power_domains_resume(display); in intel_display_power_resume_early()
2293 void intel_display_power_suspend(struct intel_display *display) in intel_display_power_suspend() argument
2295 if (DISPLAY_VER(display) >= 11) { in intel_display_power_suspend()
2296 icl_display_core_uninit(display); in intel_display_power_suspend()
2297 bxt_enable_dc9(display); in intel_display_power_suspend()
2298 } else if (display->platform.geminilake || display->platform.broxton) { in intel_display_power_suspend()
2299 bxt_display_core_uninit(display); in intel_display_power_suspend()
2300 bxt_enable_dc9(display); in intel_display_power_suspend()
2301 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_suspend()
2302 hsw_enable_pc8(display); in intel_display_power_suspend()
2306 void intel_display_power_resume(struct intel_display *display) in intel_display_power_resume() argument
2308 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_resume()
2310 if (DISPLAY_VER(display) >= 11) { in intel_display_power_resume()
2311 bxt_disable_dc9(display); in intel_display_power_resume()
2312 icl_display_core_init(display, true); in intel_display_power_resume()
2313 if (intel_dmc_has_payload(display)) { in intel_display_power_resume()
2315 skl_enable_dc6(display); in intel_display_power_resume()
2317 gen9_enable_dc5(display); in intel_display_power_resume()
2319 } else if (display->platform.geminilake || display->platform.broxton) { in intel_display_power_resume()
2320 bxt_disable_dc9(display); in intel_display_power_resume()
2321 bxt_display_core_init(display, true); in intel_display_power_resume()
2322 if (intel_dmc_has_payload(display) && in intel_display_power_resume()
2324 gen9_enable_dc5(display); in intel_display_power_resume()
2325 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_resume()
2326 hsw_disable_pc8(display); in intel_display_power_resume()
2332 struct intel_display *display = &i915->display; in intel_display_power_debug() local
2333 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_debug()
2478 intel_port_domains_for_platform(struct intel_display *display, in intel_port_domains_for_platform() argument
2482 if (DISPLAY_VER(display) >= 13) { in intel_port_domains_for_platform()
2485 } else if (DISPLAY_VER(display) >= 12) { in intel_port_domains_for_platform()
2488 } else if (DISPLAY_VER(display) >= 11) { in intel_port_domains_for_platform()
2498 intel_port_domains_for_port(struct intel_display *display, enum port port) in intel_port_domains_for_port() argument
2504 intel_port_domains_for_platform(display, &domains, &domains_size); in intel_port_domains_for_port()
2515 struct intel_display *display = &i915->display; in intel_display_power_ddi_io_domain() local
2516 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); in intel_display_power_ddi_io_domain()
2518 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) in intel_display_power_ddi_io_domain()
2527 struct intel_display *display = &i915->display; in intel_display_power_ddi_lanes_domain() local
2528 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); in intel_display_power_ddi_lanes_domain()
2530 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) in intel_display_power_ddi_lanes_domain()
2537 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) in intel_port_domains_for_aux_ch() argument
2543 intel_port_domains_for_platform(display, &domains, &domains_size); in intel_port_domains_for_aux_ch()
2554 struct intel_display *display = &i915->display; in intel_display_power_aux_io_domain() local
2555 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_aux_io_domain()
2557 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) in intel_display_power_aux_io_domain()
2566 struct intel_display *display = &i915->display; in intel_display_power_legacy_aux_domain() local
2567 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_legacy_aux_domain()
2569 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) in intel_display_power_legacy_aux_domain()
2578 struct intel_display *display = &i915->display; in intel_display_power_tbt_aux_domain() local
2579 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_tbt_aux_domain()
2581 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) in intel_display_power_tbt_aux_domain()