Lines Matching full:start
54 u32 start; member
59 { .start = 0x60000, .end = 0x7ffff },
64 { .start = 0x45500 }, /* DC_STATE_SEL */
65 { .start = 0x457a0, .end = 0x457b0 }, /* DC*_RESIDENCY_COUNTER */
66 { .start = 0x45504 }, /* DC_STATE_EN */
67 { .start = 0x45400, .end = 0x4540c }, /* PWR_WELL_CTL_* */
68 { .start = 0x454f0 }, /* RETENTION_CTRL */
71 { .start = 0x44300 },
72 { .start = 0x44304 },
73 { .start = 0x44f00 },
74 { .start = 0x44f04 },
75 { .start = 0x44fe8 },
76 { .start = 0x45008 },
78 { .start = 0x46070 }, /* CDCLK_PLL_ENABLE */
79 { .start = 0x46000 }, /* CDCLK_CTL */
80 { .start = 0x46008 }, /* CDCLK_SQUASH_CTL */
83 { .start = 0x6fa88 },
84 { .start = 0x6fb88 },
86 { .start = 0x46430 }, /* CHICKEN_DCPR_1 */
87 { .start = 0x46434 }, /* CHICKEN_DCPR_2 */
88 { .start = 0x454a0 }, /* CHICKEN_DCPR_4 */
89 { .start = 0x42084 }, /* CHICKEN_MISC_2 */
90 { .start = 0x42088 }, /* CHICKEN_MISC_3 */
91 { .start = 0x46160 }, /* CMTG_CLK_SEL */
92 { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */
98 { .start = 0x454a0 }, /* CHICKEN_DCPR_4 */
100 { .start = 0x45504 }, /* DC_STATE_EN */
103 { .start = 0x44300 },
104 { .start = 0x44304 },
105 { .start = 0x44f00 },
106 { .start = 0x44f04 },
107 { .start = 0x44fe8 },
108 { .start = 0x45008 },
110 { .start = 0x46070 }, /* CDCLK_PLL_ENABLE */
111 { .start = 0x46000 }, /* CDCLK_CTL */
112 { .start = 0x46008 }, /* CDCLK_SQUASH_CTL */
113 { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */
116 { .start = 0x70000 },
117 { .start = 0x70004 },
118 { .start = 0x70014 },
119 { .start = 0x70018 },
120 { .start = 0x71000 },
121 { .start = 0x71004 },
122 { .start = 0x71014 },
123 { .start = 0x71018 },
124 { .start = 0x72000 },
125 { .start = 0x72004 },
126 { .start = 0x72014 },
127 { .start = 0x72018 },
128 { .start = 0x73000 },
129 { .start = 0x73004 },
130 { .start = 0x73014 },
131 { .start = 0x73018 },
132 { .start = 0x7b000 },
133 { .start = 0x7b004 },
134 { .start = 0x7b014 },
135 { .start = 0x7b018 },
136 { .start = 0x7c000 },
137 { .start = 0x7c004 },
138 { .start = 0x7c014 },
139 { .start = 0x7c018 },
223 for (int i = 0; ranges[i].start; i++) { in intel_dmc_wl_reg_in_range()
224 u32 end = ranges[i].end ?: ranges[i].start; in intel_dmc_wl_reg_in_range()
226 if (ranges[i].start <= offset && offset <= end) in intel_dmc_wl_reg_in_range()