Lines Matching full:display
28 * compressing the amount of memory used by the display. It is total
33 * and having fewer memory pages opened and accessed for refreshing the display.
94 struct intel_display *display; member
158 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, in skl_fbc_min_cfb_stride() argument
172 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
186 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, in _intel_fbc_cfb_stride() argument
195 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
196 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); in _intel_fbc_cfb_stride()
203 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_stride() local
208 return _intel_fbc_cfb_stride(display, cpp, width, stride); in intel_fbc_cfb_stride()
216 static unsigned int intel_fbc_max_cfb_height(struct intel_display *display) in intel_fbc_max_cfb_height() argument
218 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_max_cfb_height()
220 if (DISPLAY_VER(display) >= 8) in intel_fbc_max_cfb_height()
222 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in intel_fbc_max_cfb_height()
228 static unsigned int _intel_fbc_cfb_size(struct intel_display *display, in _intel_fbc_cfb_size() argument
231 return min(height, intel_fbc_max_cfb_height(display)) * stride; in _intel_fbc_cfb_size()
236 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_size() local
239 return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state)); in intel_fbc_cfb_size()
244 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_override_cfb_stride() local
257 (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) in intel_fbc_override_cfb_stride()
263 static bool intel_fbc_has_fences(struct intel_display *display) in intel_fbc_has_fences() argument
265 struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); in intel_fbc_has_fences()
273 struct intel_display *display = fbc->display; in i8xx_fbc_ctl() local
274 struct drm_i915_private *i915 = to_i915(display->drm); in i8xx_fbc_ctl()
281 if (DISPLAY_VER(display) == 2) in i8xx_fbc_ctl()
315 struct intel_display *display = fbc->display; in i8xx_fbc_deactivate() local
319 fbc_ctl = intel_de_read(display, FBC_CONTROL); in i8xx_fbc_deactivate()
324 intel_de_write(display, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
327 if (intel_de_wait_for_clear(display, FBC_STATUS, in i8xx_fbc_deactivate()
329 drm_dbg_kms(display->drm, "FBC idle timed out\n"); in i8xx_fbc_deactivate()
337 struct intel_display *display = fbc->display; in i8xx_fbc_activate() local
342 intel_de_write(display, FBC_TAG(i), 0); in i8xx_fbc_activate()
344 if (DISPLAY_VER(display) == 4) { in i8xx_fbc_activate()
345 intel_de_write(display, FBC_CONTROL2, in i8xx_fbc_activate()
347 intel_de_write(display, FBC_FENCE_OFF, in i8xx_fbc_activate()
351 intel_de_write(display, FBC_CONTROL, in i8xx_fbc_activate()
357 return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN; in i8xx_fbc_is_active()
362 return intel_de_read(fbc->display, FBC_STATUS) & in i8xx_fbc_is_compressing()
370 struct drm_i915_private *dev_priv = to_i915(fbc->display->drm); in i8xx_fbc_nuke()
378 struct intel_display *display = fbc->display; in i8xx_fbc_program_cfb() local
379 struct drm_i915_private *i915 = to_i915(display->drm); in i8xx_fbc_program_cfb()
381 drm_WARN_ON(display->drm, in i8xx_fbc_program_cfb()
385 drm_WARN_ON(display->drm, in i8xx_fbc_program_cfb()
408 struct drm_i915_private *dev_priv = to_i915(fbc->display->drm); in i965_fbc_nuke()
441 struct intel_display *display = fbc->display; in g4x_dpfc_ctl() local
442 struct drm_i915_private *i915 = to_i915(display->drm); in g4x_dpfc_ctl()
454 if (DISPLAY_VER(display) < 6) in g4x_dpfc_ctl()
464 struct intel_display *display = fbc->display; in g4x_fbc_activate() local
466 intel_de_write(display, DPFC_FENCE_YOFF, in g4x_fbc_activate()
469 intel_de_write(display, DPFC_CONTROL, in g4x_fbc_activate()
475 struct intel_display *display = fbc->display; in g4x_fbc_deactivate() local
479 dpfc_ctl = intel_de_read(display, DPFC_CONTROL); in g4x_fbc_deactivate()
482 intel_de_write(display, DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
488 return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN; in g4x_fbc_is_active()
493 return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK; in g4x_fbc_is_compressing()
498 struct intel_display *display = fbc->display; in g4x_fbc_program_cfb() local
500 intel_de_write(display, DPFC_CB_BASE, in g4x_fbc_program_cfb()
516 struct intel_display *display = fbc->display; in ilk_fbc_activate() local
518 intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id), in ilk_fbc_activate()
521 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), in ilk_fbc_activate()
527 struct intel_display *display = fbc->display; in ilk_fbc_deactivate() local
531 dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); in ilk_fbc_deactivate()
534 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); in ilk_fbc_deactivate()
540 return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN; in ilk_fbc_is_active()
545 return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK; in ilk_fbc_is_compressing()
550 struct intel_display *display = fbc->display; in ilk_fbc_program_cfb() local
552 intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id), in ilk_fbc_program_cfb()
568 struct intel_display *display = fbc->display; in snb_fbc_program_fence() local
574 intel_de_write(display, SNB_DPFC_CTL_SA, ctl); in snb_fbc_program_fence()
575 intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); in snb_fbc_program_fence()
587 struct intel_display *display = fbc->display; in snb_fbc_nuke() local
589 intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE); in snb_fbc_nuke()
590 intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id)); in snb_fbc_nuke()
605 struct intel_display *display = fbc->display; in glk_fbc_program_cfb_stride() local
612 intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val); in glk_fbc_program_cfb_stride()
618 struct intel_display *display = fbc->display; in skl_fbc_program_cfb_stride() local
621 /* Display WA #0529: skl, kbl, bxt. */ in skl_fbc_program_cfb_stride()
626 intel_de_rmw(display, CHICKEN_MISC_4, in skl_fbc_program_cfb_stride()
634 struct intel_display *display = fbc->display; in ivb_dpfc_ctl() local
635 struct drm_i915_private *i915 = to_i915(display->drm); in ivb_dpfc_ctl()
643 if (DISPLAY_VER(display) >= 20) in ivb_dpfc_ctl()
657 struct intel_display *display = fbc->display; in ivb_fbc_activate() local
660 if (DISPLAY_VER(display) >= 10) in ivb_fbc_activate()
662 else if (DISPLAY_VER(display) == 9) in ivb_fbc_activate()
665 if (intel_fbc_has_fences(display)) in ivb_fbc_activate()
670 if (DISPLAY_VER(display) >= 20) in ivb_fbc_activate()
671 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); in ivb_fbc_activate()
673 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), in ivb_fbc_activate()
679 return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB; in ivb_fbc_is_compressing()
685 intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id), in ivb_fbc_set_false_color()
730 struct intel_display *display = fbc->display; in intel_fbc_nuke() local
733 drm_WARN_ON(display->drm, fbc->flip_pending); in intel_fbc_nuke()
760 static u64 intel_fbc_cfb_base_max(struct intel_display *display) in intel_fbc_cfb_base_max() argument
762 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_cfb_base_max()
764 if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in intel_fbc_cfb_base_max()
770 static u64 intel_fbc_stolen_end(struct intel_display *display) in intel_fbc_stolen_end() argument
772 struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); in intel_fbc_stolen_end()
780 (DISPLAY_VER(display) == 9 && !IS_BROXTON(i915))) in intel_fbc_stolen_end()
785 return min(end, intel_fbc_cfb_base_max(display)); in intel_fbc_stolen_end()
793 static int intel_fbc_max_limit(struct intel_display *display) in intel_fbc_max_limit() argument
795 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_max_limit()
811 struct intel_display *display = fbc->display; in find_compression_limit() local
812 struct drm_i915_private *i915 = to_i915(display->drm); in find_compression_limit()
813 u64 end = intel_fbc_stolen_end(display); in find_compression_limit()
824 for (; limit <= intel_fbc_max_limit(display); limit <<= 1) { in find_compression_limit()
837 struct intel_display *display = fbc->display; in intel_fbc_alloc_cfb() local
838 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_alloc_cfb()
841 drm_WARN_ON(display->drm, in intel_fbc_alloc_cfb()
843 drm_WARN_ON(display->drm, in intel_fbc_alloc_cfb()
846 if (DISPLAY_VER(display) < 5 && !IS_G4X(i915)) { in intel_fbc_alloc_cfb()
857 drm_info_once(display->drm, in intel_fbc_alloc_cfb()
862 drm_dbg_kms(display->drm, in intel_fbc_alloc_cfb()
872 drm_info_once(display->drm, in intel_fbc_alloc_cfb()
884 struct intel_display *display = fbc->display; in intel_fbc_program_workarounds() local
885 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_program_workarounds()
890 * Display WA #0883: skl,bxt in intel_fbc_program_workarounds()
892 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
900 * Display WA #0873: skl,kbl,cfl in intel_fbc_program_workarounds()
902 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
907 if (IS_DISPLAY_VER(display, 11, 12)) in intel_fbc_program_workarounds()
908 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
912 if (DISPLAY_VER(display) >= 11 && !IS_DG2(i915)) in intel_fbc_program_workarounds()
913 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
919 struct intel_display *display = fbc->display; in __intel_fbc_cleanup_cfb() local
920 struct drm_i915_private *i915 = to_i915(display->drm); in __intel_fbc_cleanup_cfb()
931 void intel_fbc_cleanup(struct intel_display *display) in intel_fbc_cleanup() argument
936 for_each_intel_fbc(display, fbc, fbc_id) { in intel_fbc_cleanup()
974 /* Display WA #1105: skl,bxt,kbl,cfl,glk */ in skl_fbc_stride_is_valid()
988 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in stride_is_valid() local
989 struct drm_i915_private *i915 = to_i915(display->drm); in stride_is_valid()
991 if (DISPLAY_VER(display) >= 11) in stride_is_valid()
993 else if (DISPLAY_VER(display) >= 9) in stride_is_valid()
995 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in stride_is_valid()
997 else if (DISPLAY_VER(display) == 4) in stride_is_valid()
1005 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in i8xx_fbc_pixel_format_is_valid() local
1015 if (DISPLAY_VER(display) == 2) in i8xx_fbc_pixel_format_is_valid()
1025 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in g4x_fbc_pixel_format_is_valid() local
1026 struct drm_i915_private *i915 = to_i915(display->drm); in g4x_fbc_pixel_format_is_valid()
1061 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in pixel_format_is_valid() local
1062 struct drm_i915_private *i915 = to_i915(display->drm); in pixel_format_is_valid()
1064 if (DISPLAY_VER(display) >= 20) in pixel_format_is_valid()
1066 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in pixel_format_is_valid()
1096 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in rotation_is_valid() local
1097 struct drm_i915_private *i915 = to_i915(display->drm); in rotation_is_valid()
1099 if (DISPLAY_VER(display) >= 9) in rotation_is_valid()
1101 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in rotation_is_valid()
1107 static void intel_fbc_max_surface_size(struct intel_display *display, in intel_fbc_max_surface_size() argument
1110 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_max_surface_size()
1112 if (DISPLAY_VER(display) >= 11) { in intel_fbc_max_surface_size()
1115 } else if (DISPLAY_VER(display) >= 10) { in intel_fbc_max_surface_size()
1118 } else if (DISPLAY_VER(display) >= 7) { in intel_fbc_max_surface_size()
1121 } else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) { in intel_fbc_max_surface_size()
1132 * programmed as the display plane base address register. It does not look at
1138 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_surface_size_ok() local
1141 intel_fbc_max_surface_size(display, &max_w, &max_h); in intel_fbc_surface_size_ok()
1151 static void intel_fbc_max_plane_size(struct intel_display *display, in intel_fbc_max_plane_size() argument
1154 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_max_plane_size()
1156 if (DISPLAY_VER(display) >= 10) { in intel_fbc_max_plane_size()
1159 } else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(i915)) { in intel_fbc_max_plane_size()
1162 } else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) { in intel_fbc_max_plane_size()
1173 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_plane_size_valid() local
1176 intel_fbc_max_plane_size(display, &max_w, &max_h); in intel_fbc_plane_size_valid()
1198 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in tiling_is_valid() local
1200 if (DISPLAY_VER(display) >= 9) in tiling_is_valid()
1210 struct intel_display *display = to_intel_display(state->base.dev); in intel_fbc_update_state() local
1228 drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE && in intel_fbc_update_state()
1229 !intel_fbc_has_fences(display)); in intel_fbc_update_state()
1243 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_is_fence_ok() local
1257 return DISPLAY_VER(display) >= 9 || in intel_fbc_is_fence_ok()
1282 struct intel_display *display = to_intel_display(state->base.dev); in intel_fbc_check_plane() local
1283 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_check_plane()
1304 if (!display->params.enable_fbc) { in intel_fbc_check_plane()
1338 * Display 12+ is not supporting FBC with PSR2. in intel_fbc_check_plane()
1342 if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && in intel_fbc_check_plane()
1349 if ((IS_DISPLAY_VER(display, 12, 13) || in intel_fbc_check_plane()
1376 if (DISPLAY_VER(display) < 20 && in intel_fbc_check_plane()
1398 if (DISPLAY_VER(display) >= 9 && in intel_fbc_check_plane()
1405 if (DISPLAY_VER(display) >= 11 && in intel_fbc_check_plane()
1481 struct intel_display *display = to_intel_display(state->base.dev); in __intel_fbc_pre_update() local
1495 * Display WA #1198: glk+ in __intel_fbc_pre_update()
1507 if (fbc->activated && DISPLAY_VER(display) >= 10) in __intel_fbc_pre_update()
1541 struct intel_display *display = fbc->display; in __intel_fbc_disable() local
1545 drm_WARN_ON(display->drm, fbc->active); in __intel_fbc_disable()
1547 drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n", in __intel_fbc_disable()
1624 for_each_intel_fbc(&i915->display, fbc, fbc_id) in intel_fbc_invalidate()
1663 for_each_intel_fbc(&i915->display, fbc, fbc_id) in intel_fbc_flush()
1688 struct intel_display *display = to_intel_display(state->base.dev); in __intel_fbc_enable() local
1707 drm_WARN_ON(display->drm, fbc->active); in __intel_fbc_enable()
1729 drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n", in __intel_fbc_enable()
1747 struct intel_display *display = to_intel_display(crtc->base.dev); in intel_fbc_disable() local
1750 for_each_intel_plane(display->drm, plane) { in intel_fbc_disable()
1795 struct intel_display *display = fbc->display; in intel_fbc_underrun_work_fn() local
1803 drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n"); in intel_fbc_underrun_work_fn()
1808 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe)); in intel_fbc_underrun_work_fn()
1816 struct intel_display *display = fbc->display; in __intel_fbc_reset_underrun() local
1823 drm_dbg_kms(display->drm, in __intel_fbc_reset_underrun()
1834 * @display: display
1839 void intel_fbc_reset_underrun(struct intel_display *display) in intel_fbc_reset_underrun() argument
1844 for_each_intel_fbc(display, fbc, fbc_id) in intel_fbc_reset_underrun()
1850 struct drm_i915_private *i915 = to_i915(fbc->display->drm); in __intel_fbc_handle_fifo_underrun_irq()
1868 * @display: display
1880 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) in intel_fbc_handle_fifo_underrun_irq() argument
1885 for_each_intel_fbc(display, fbc, fbc_id) in intel_fbc_handle_fifo_underrun_irq()
1898 static int intel_sanitize_fbc_option(struct intel_display *display) in intel_sanitize_fbc_option() argument
1900 struct drm_i915_private *i915 = to_i915(display->drm); in intel_sanitize_fbc_option()
1902 if (display->params.enable_fbc >= 0) in intel_sanitize_fbc_option()
1903 return !!display->params.enable_fbc; in intel_sanitize_fbc_option()
1905 if (!HAS_FBC(display)) in intel_sanitize_fbc_option()
1908 if (IS_BROADWELL(i915) || DISPLAY_VER(display) >= 9) in intel_sanitize_fbc_option()
1919 static struct intel_fbc *intel_fbc_create(struct intel_display *display, in intel_fbc_create() argument
1922 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_create()
1930 fbc->display = display; in intel_fbc_create()
1934 if (DISPLAY_VER(display) >= 7) in intel_fbc_create()
1936 else if (DISPLAY_VER(display) == 6) in intel_fbc_create()
1938 else if (DISPLAY_VER(display) == 5) in intel_fbc_create()
1942 else if (DISPLAY_VER(display) == 4) in intel_fbc_create()
1952 * @display: display
1956 void intel_fbc_init(struct intel_display *display) in intel_fbc_init() argument
1960 display->params.enable_fbc = intel_sanitize_fbc_option(display); in intel_fbc_init()
1961 drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n", in intel_fbc_init()
1962 display->params.enable_fbc); in intel_fbc_init()
1964 for_each_fbc_id(display, fbc_id) in intel_fbc_init()
1965 display->fbc[fbc_id] = intel_fbc_create(display, fbc_id); in intel_fbc_init()
1970 * @display: display
1976 void intel_fbc_sanitize(struct intel_display *display) in intel_fbc_sanitize() argument
1981 for_each_intel_fbc(display, fbc, fbc_id) { in intel_fbc_sanitize()
1990 struct intel_display *display = fbc->display; in intel_fbc_debugfs_status_show() local
1991 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_debugfs_status_show()
1995 drm_modeset_lock_all(display->drm); in intel_fbc_debugfs_status_show()
2008 for_each_intel_plane(display->drm, plane) { in intel_fbc_debugfs_status_show()
2024 drm_modeset_unlock_all(display->drm); in intel_fbc_debugfs_status_show()
2081 void intel_fbc_debugfs_register(struct intel_display *display) in intel_fbc_debugfs_register() argument
2083 struct drm_minor *minor = display->drm->primary; in intel_fbc_debugfs_register()
2086 fbc = display->fbc[INTEL_FBC_A]; in intel_fbc_debugfs_register()