Lines Matching full:display
34 #include <drm/display/drm_hdcp_helper.h>
51 struct intel_display *display; member
152 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, in get_gmbus_pin() argument
155 struct drm_i915_private *i915 = to_i915(display->drm); in get_gmbus_pin()
177 } else if (DISPLAY_VER(display) == 9) { in get_gmbus_pin()
194 bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin) in intel_gmbus_is_valid_pin() argument
196 return get_gmbus_pin(display, pin); in intel_gmbus_is_valid_pin()
210 intel_gmbus_reset(struct intel_display *display) in intel_gmbus_reset() argument
212 intel_de_write(display, GMBUS0(display), 0); in intel_gmbus_reset()
213 intel_de_write(display, GMBUS4(display), 0); in intel_gmbus_reset()
216 static void pnv_gmbus_clock_gating(struct intel_display *display, in pnv_gmbus_clock_gating() argument
220 intel_de_rmw(display, DSPCLK_GATE_D(display), in pnv_gmbus_clock_gating()
225 static void pch_gmbus_clock_gating(struct intel_display *display, in pch_gmbus_clock_gating() argument
228 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in pch_gmbus_clock_gating()
233 static void bxt_gmbus_clock_gating(struct intel_display *display, in bxt_gmbus_clock_gating() argument
236 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, in bxt_gmbus_clock_gating()
242 struct intel_display *display = bus->display; in get_reserved() local
243 struct drm_i915_private *i915 = to_i915(display->drm); in get_reserved()
248 reserved = intel_de_read_notrace(display, bus->gpio_reg) & in get_reserved()
257 struct intel_display *display = bus->display; in get_clock() local
260 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); in get_clock()
261 intel_de_write_notrace(display, bus->gpio_reg, reserved); in get_clock()
263 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; in get_clock()
269 struct intel_display *display = bus->display; in get_data() local
272 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); in get_data()
273 intel_de_write_notrace(display, bus->gpio_reg, reserved); in get_data()
275 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; in get_data()
281 struct intel_display *display = bus->display; in set_clock() local
291 intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits); in set_clock()
292 intel_de_posting_read(display, bus->gpio_reg); in set_clock()
298 struct intel_display *display = bus->display; in set_data() local
308 intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits); in set_data()
309 intel_de_posting_read(display, bus->gpio_reg); in set_data()
316 struct intel_display *display = bus->display; in intel_gpio_pre_xfer() local
317 struct drm_i915_private *i915 = to_i915(display->drm); in intel_gpio_pre_xfer()
319 intel_gmbus_reset(display); in intel_gpio_pre_xfer()
322 pnv_gmbus_clock_gating(display, false); in intel_gpio_pre_xfer()
334 struct intel_display *display = bus->display; in intel_gpio_post_xfer() local
335 struct drm_i915_private *i915 = to_i915(display->drm); in intel_gpio_post_xfer()
341 pnv_gmbus_clock_gating(display, true); in intel_gpio_post_xfer()
364 static bool has_gmbus_irq(struct intel_display *display) in has_gmbus_irq() argument
366 struct drm_i915_private *i915 = to_i915(display->drm); in has_gmbus_irq()
371 return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915); in has_gmbus_irq()
374 static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en) in gmbus_wait() argument
384 if (!has_gmbus_irq(display)) in gmbus_wait()
387 add_wait_queue(&display->gmbus.wait_queue, &wait); in gmbus_wait()
388 intel_de_write_fw(display, GMBUS4(display), irq_en); in gmbus_wait()
391 ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status, in gmbus_wait()
394 ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status, in gmbus_wait()
397 intel_de_write_fw(display, GMBUS4(display), 0); in gmbus_wait()
398 remove_wait_queue(&display->gmbus.wait_queue, &wait); in gmbus_wait()
407 gmbus_wait_idle(struct intel_display *display) in gmbus_wait_idle() argument
415 if (has_gmbus_irq(display)) in gmbus_wait_idle()
418 add_wait_queue(&display->gmbus.wait_queue, &wait); in gmbus_wait_idle()
419 intel_de_write_fw(display, GMBUS4(display), irq_enable); in gmbus_wait_idle()
421 ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10); in gmbus_wait_idle()
423 intel_de_write_fw(display, GMBUS4(display), 0); in gmbus_wait_idle()
424 remove_wait_queue(&display->gmbus.wait_queue, &wait); in gmbus_wait_idle()
429 static unsigned int gmbus_max_xfer_size(struct intel_display *display) in gmbus_max_xfer_size() argument
431 return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : in gmbus_max_xfer_size()
436 gmbus_xfer_read_chunk(struct intel_display *display, in gmbus_xfer_read_chunk() argument
441 bool burst_read = len > gmbus_max_xfer_size(display); in gmbus_xfer_read_chunk()
454 intel_de_write_fw(display, GMBUS0(display), in gmbus_xfer_read_chunk()
458 intel_de_write_fw(display, GMBUS1(display), in gmbus_xfer_read_chunk()
464 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); in gmbus_xfer_read_chunk()
468 val = intel_de_read_fw(display, GMBUS3(display)); in gmbus_xfer_read_chunk()
479 intel_de_write_fw(display, GMBUS0(display), gmbus0_reg); in gmbus_xfer_read_chunk()
496 gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg, in gmbus_xfer_read() argument
505 if (HAS_GMBUS_BURST_READ(display)) in gmbus_xfer_read()
508 len = min(rx_size, gmbus_max_xfer_size(display)); in gmbus_xfer_read()
510 ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len, in gmbus_xfer_read()
523 gmbus_xfer_write_chunk(struct intel_display *display, in gmbus_xfer_write_chunk() argument
536 intel_de_write_fw(display, GMBUS3(display), val); in gmbus_xfer_write_chunk()
537 intel_de_write_fw(display, GMBUS1(display), in gmbus_xfer_write_chunk()
547 intel_de_write_fw(display, GMBUS3(display), val); in gmbus_xfer_write_chunk()
549 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); in gmbus_xfer_write_chunk()
558 gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg, in gmbus_xfer_write() argument
567 len = min(tx_size, gmbus_max_xfer_size(display)); in gmbus_xfer_write()
569 ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len, in gmbus_xfer_write()
596 gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs, in gmbus_index_xfer() argument
612 intel_de_write_fw(display, GMBUS5(display), gmbus5); in gmbus_index_xfer()
615 ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg, in gmbus_index_xfer()
618 ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index); in gmbus_index_xfer()
622 intel_de_write_fw(display, GMBUS5(display), 0); in gmbus_index_xfer()
632 struct intel_display *display = bus->display; in do_gmbus_xfer() local
633 struct drm_i915_private *i915 = to_i915(display->drm); in do_gmbus_xfer()
637 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ in do_gmbus_xfer()
639 bxt_gmbus_clock_gating(display, false); in do_gmbus_xfer()
641 pch_gmbus_clock_gating(display, false); in do_gmbus_xfer()
644 intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0); in do_gmbus_xfer()
649 ret = gmbus_index_xfer(display, &msgs[i], in do_gmbus_xfer()
653 ret = gmbus_xfer_read(display, &msgs[i], in do_gmbus_xfer()
656 ret = gmbus_xfer_write(display, &msgs[i], 0); in do_gmbus_xfer()
660 ret = gmbus_wait(display, in do_gmbus_xfer()
672 intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); in do_gmbus_xfer()
678 if (gmbus_wait_idle(display)) { in do_gmbus_xfer()
679 drm_dbg_kms(display->drm, in do_gmbus_xfer()
684 intel_de_write_fw(display, GMBUS0(display), 0); in do_gmbus_xfer()
703 if (gmbus_wait_idle(display)) { in do_gmbus_xfer()
704 drm_dbg_kms(display->drm, in do_gmbus_xfer()
714 intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT); in do_gmbus_xfer()
715 intel_de_write_fw(display, GMBUS1(display), 0); in do_gmbus_xfer()
716 intel_de_write_fw(display, GMBUS0(display), 0); in do_gmbus_xfer()
718 drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", in do_gmbus_xfer()
729 drm_dbg_kms(display->drm, in do_gmbus_xfer()
738 drm_dbg_kms(display->drm, in do_gmbus_xfer()
741 intel_de_write_fw(display, GMBUS0(display), 0); in do_gmbus_xfer()
750 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ in do_gmbus_xfer()
752 bxt_gmbus_clock_gating(display, true); in do_gmbus_xfer()
754 pch_gmbus_clock_gating(display, true); in do_gmbus_xfer()
763 struct intel_display *display = bus->display; in gmbus_xfer() local
764 struct drm_i915_private *i915 = to_i915(display->drm); in gmbus_xfer()
788 struct intel_display *display = bus->display; in intel_gmbus_output_aksv() local
789 struct drm_i915_private *i915 = to_i915(display->drm); in intel_gmbus_output_aksv()
810 mutex_lock(&display->gmbus.mutex); in intel_gmbus_output_aksv()
819 mutex_unlock(&display->gmbus.mutex); in intel_gmbus_output_aksv()
843 struct intel_display *display = bus->display; in gmbus_lock_bus() local
845 mutex_lock(&display->gmbus.mutex); in gmbus_lock_bus()
852 struct intel_display *display = bus->display; in gmbus_trylock_bus() local
854 return mutex_trylock(&display->gmbus.mutex); in gmbus_trylock_bus()
861 struct intel_display *display = bus->display; in gmbus_unlock_bus() local
863 mutex_unlock(&display->gmbus.mutex); in gmbus_unlock_bus()
874 * @display: display device
876 int intel_gmbus_setup(struct intel_display *display) in intel_gmbus_setup() argument
878 struct drm_i915_private *i915 = to_i915(display->drm); in intel_gmbus_setup()
879 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in intel_gmbus_setup()
884 display->gmbus.mmio_base = VLV_DISPLAY_BASE; in intel_gmbus_setup()
885 else if (!HAS_GMCH(display)) in intel_gmbus_setup()
887 * Broxton uses the same PCH offsets for South Display Engine, in intel_gmbus_setup()
890 display->gmbus.mmio_base = PCH_DISPLAY_BASE; in intel_gmbus_setup()
892 mutex_init(&display->gmbus.mutex); in intel_gmbus_setup()
893 init_waitqueue_head(&display->gmbus.wait_queue); in intel_gmbus_setup()
895 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { in intel_gmbus_setup()
899 gmbus_pin = get_gmbus_pin(display, pin); in intel_gmbus_setup()
915 bus->display = display; in intel_gmbus_setup()
933 intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio)); in intel_gmbus_setup()
941 display->gmbus.bus[pin] = bus; in intel_gmbus_setup()
944 intel_gmbus_reset(display); in intel_gmbus_setup()
949 intel_gmbus_teardown(display); in intel_gmbus_setup()
954 struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display, in intel_gmbus_get_adapter() argument
957 if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) || in intel_gmbus_get_adapter()
958 !display->gmbus.bus[pin])) in intel_gmbus_get_adapter()
961 return &display->gmbus.bus[pin]->adapter; in intel_gmbus_get_adapter()
967 struct intel_display *display = bus->display; in intel_gmbus_force_bit() local
969 mutex_lock(&display->gmbus.mutex); in intel_gmbus_force_bit()
972 drm_dbg_kms(display->drm, in intel_gmbus_force_bit()
977 mutex_unlock(&display->gmbus.mutex); in intel_gmbus_force_bit()
987 void intel_gmbus_teardown(struct intel_display *display) in intel_gmbus_teardown() argument
991 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { in intel_gmbus_teardown()
994 bus = display->gmbus.bus[pin]; in intel_gmbus_teardown()
1001 display->gmbus.bus[pin] = NULL; in intel_gmbus_teardown()
1005 void intel_gmbus_irq_handler(struct intel_display *display) in intel_gmbus_irq_handler() argument
1007 wake_up_all(&display->gmbus.wait_queue); in intel_gmbus_irq_handler()