405 			    u32 val, bool sel_update_enabled)  in psr_event_print()
463 			u32 val;  in intel_psr_irq_handler()  local
497 	u8 val = 8; /* assume the worst if we can't read the value */  in intel_dp_get_sink_sync_latency()  local
743 	u8 val = DP_PANEL_REPLAY_ENABLE |  in _panel_replay_enable_sink()  local
770 	u8 val = 0;  in _psr_enable_sink()  local
799 	u8 val;  in intel_psr_enable_sink_alpm()  local
835 	u32 val = 0;  in intel_psr1_get_tp_time()  local
907 	u32 val = EDP_PSR_ENABLE;  in hsw_activate_psr1()  local
936 	u32 val = 0;  in intel_psr2_get_tp_time()  local
987 		u32 val = psr->su_region_et_enabled ?  in dg2_activate_panel_replay()  local
1010 	u32 val = EDP_PSR2_ENABLE;  in hsw_activate_psr2()  local
1715 	u32 val;  in intel_psr_get_config()  local
1941 	u32 val;  in psr_interrupt_error_check()  local
1972 	u32 val;  in intel_psr_enable_locked()  local
2030 	u32 val;  in intel_psr_exit()  local
2378 	u32 val = man_trk_ctl_enable_bit_get(display);  in psr2_man_trk_ctl_calc()  local
3035 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)  in intel_psr_debug_set()
3129 		u32 val;  in _psr_invalidate_handle()  local
3234 				u32 val = man_trk_ctl_enable_bit_get(display) |  in _psr_flush_handle()  local
3405 	u8 val;  in psr_alpm_check()  local
3432 	u8 val;  in psr_capability_changed_check()  local
3464 	const u8 errors = DP_PSR_RFB_STORAGE_ERROR |  in intel_psr_short_pulse()  local
3615 	u32 val, status_val;  in psr_source_status()  local
3716 	u32 val, psr2_ctl;  in intel_psr_status()  local
3833 i915_edp_psr_debug_set(void *data, u64 val)  in i915_edp_psr_debug_set()
3861 i915_edp_psr_debug_get(void *data, u64 *val)  in i915_edp_psr_debug_get()