52  * Since Haswell Display controller supports Panel Self-Refresh on display
54  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
55  * when system is idle but display is on as it eliminates display refresh
57  * display is unchanged.
101  *  When unmasked (nearly) all display register writes (eg. even
230 	struct intel_display *display = to_intel_display(intel_dp);  in psr_global_enabled()  local
235 		if (display->params.enable_psr == -1)  in psr_global_enabled()
239 		return display->params.enable_psr;  in psr_global_enabled()
249 	struct intel_display *display = to_intel_display(intel_dp);  in psr2_global_enabled()  local
256 		if (display->params.enable_psr == 1)  in psr2_global_enabled()
264 	struct intel_display *display = to_intel_display(intel_dp);  in psr2_su_region_et_global_enabled()  local
266 	if (display->params.enable_psr != -1)  in psr2_su_region_et_global_enabled()
274 	struct intel_display *display = to_intel_display(intel_dp);  in panel_replay_global_enabled()  local
276 	if ((display->params.enable_psr != -1) ||  in panel_replay_global_enabled()
284 	struct intel_display *display = to_intel_display(intel_dp);  in psr_irq_psr_error_bit_get()  local
286 	return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR :  in psr_irq_psr_error_bit_get()
292 	struct intel_display *display = to_intel_display(intel_dp);  in psr_irq_post_exit_bit_get()  local
294 	return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT :  in psr_irq_post_exit_bit_get()
300 	struct intel_display *display = to_intel_display(intel_dp);  in psr_irq_pre_entry_bit_get()  local
302 	return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY :  in psr_irq_pre_entry_bit_get()
308 	struct intel_display *display = to_intel_display(intel_dp);  in psr_irq_mask_get()  local
310 	return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK :  in psr_irq_mask_get()
314 static i915_reg_t psr_ctl_reg(struct intel_display *display,  in psr_ctl_reg()  argument
317 	if (DISPLAY_VER(display) >= 8)  in psr_ctl_reg()
318 		return EDP_PSR_CTL(display, cpu_transcoder);  in psr_ctl_reg()
323 static i915_reg_t psr_debug_reg(struct intel_display *display,  in psr_debug_reg()  argument
326 	if (DISPLAY_VER(display) >= 8)  in psr_debug_reg()
327 		return EDP_PSR_DEBUG(display, cpu_transcoder);  in psr_debug_reg()
332 static i915_reg_t psr_perf_cnt_reg(struct intel_display *display,  in psr_perf_cnt_reg()  argument
335 	if (DISPLAY_VER(display) >= 8)  in psr_perf_cnt_reg()
336 		return EDP_PSR_PERF_CNT(display, cpu_transcoder);  in psr_perf_cnt_reg()
341 static i915_reg_t psr_status_reg(struct intel_display *display,  in psr_status_reg()  argument
344 	if (DISPLAY_VER(display) >= 8)  in psr_status_reg()
345 		return EDP_PSR_STATUS(display, cpu_transcoder);  in psr_status_reg()
350 static i915_reg_t psr_imr_reg(struct intel_display *display,  in psr_imr_reg()  argument
353 	if (DISPLAY_VER(display) >= 12)  in psr_imr_reg()
354 		return TRANS_PSR_IMR(display, cpu_transcoder);  in psr_imr_reg()
359 static i915_reg_t psr_iir_reg(struct intel_display *display,  in psr_iir_reg()  argument
362 	if (DISPLAY_VER(display) >= 12)  in psr_iir_reg()
363 		return TRANS_PSR_IIR(display, cpu_transcoder);  in psr_iir_reg()
368 static i915_reg_t psr_aux_ctl_reg(struct intel_display *display,  in psr_aux_ctl_reg()  argument
371 	if (DISPLAY_VER(display) >= 8)  in psr_aux_ctl_reg()
372 		return EDP_PSR_AUX_CTL(display, cpu_transcoder);  in psr_aux_ctl_reg()
377 static i915_reg_t psr_aux_data_reg(struct intel_display *display,  in psr_aux_data_reg()  argument
380 	if (DISPLAY_VER(display) >= 8)  in psr_aux_data_reg()
381 		return EDP_PSR_AUX_DATA(display, cpu_transcoder, i);  in psr_aux_data_reg()
388 	struct intel_display *display = to_intel_display(intel_dp);  in psr_irq_control()  local
400 	intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),  in psr_irq_control()
404 static void psr_event_print(struct intel_display *display,  in psr_event_print()  argument
407 	drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val);  in psr_event_print()
409 		drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n");  in psr_event_print()
411 		drm_dbg_kms(display->drm, "\tPSR2 disabled\n");  in psr_event_print()
413 		drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n");  in psr_event_print()
415 		drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n");  in psr_event_print()
417 		drm_dbg_kms(display->drm, "\tGraphics reset\n");  in psr_event_print()
419 		drm_dbg_kms(display->drm, "\tPCH interrupt\n");  in psr_event_print()
421 		drm_dbg_kms(display->drm, "\tMemory up\n");  in psr_event_print()
423 		drm_dbg_kms(display->drm, "\tFront buffer modification\n");  in psr_event_print()
425 		drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n");  in psr_event_print()
427 		drm_dbg_kms(display->drm, "\tPIPE registers updated\n");  in psr_event_print()
429 		drm_dbg_kms(display->drm, "\tRegister updated\n");  in psr_event_print()
431 		drm_dbg_kms(display->drm, "\tHDCP enabled\n");  in psr_event_print()
433 		drm_dbg_kms(display->drm, "\tKVMR session enabled\n");  in psr_event_print()
435 		drm_dbg_kms(display->drm, "\tVBI enabled\n");  in psr_event_print()
437 		drm_dbg_kms(display->drm, "\tLPSP mode exited\n");  in psr_event_print()
439 		drm_dbg_kms(display->drm, "\tPSR disabled\n");  in psr_event_print()
444 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_irq_handler()  local
445 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_psr_irq_handler()
451 		drm_dbg_kms(display->drm,  in intel_psr_irq_handler()
458 		drm_dbg_kms(display->drm,  in intel_psr_irq_handler()
462 		if (DISPLAY_VER(display) >= 9) {  in intel_psr_irq_handler()
469 			psr_event_print(display, val, intel_dp->psr.sel_update_enabled);  in intel_psr_irq_handler()
474 		drm_warn(display->drm, "[transcoder %s] PSR aux error\n",  in intel_psr_irq_handler()
487 		intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),  in intel_psr_irq_handler()
496 	struct intel_display *display = to_intel_display(intel_dp);  in intel_dp_get_sink_sync_latency()  local
503 		drm_dbg_kms(display->drm,  in intel_dp_get_sink_sync_latency()
544 	struct intel_display *display = to_intel_display(intel_dp);  in intel_dp_get_su_granularity()  local
570 		drm_dbg_kms(display->drm,  in intel_dp_get_su_granularity()
583 		drm_dbg_kms(display->drm,  in intel_dp_get_su_granularity()
597 	struct intel_display *display = to_intel_display(intel_dp);  in _panel_replay_init_dpcd()  local
601 			drm_dbg_kms(display->drm,  in _panel_replay_init_dpcd()
607 			drm_dbg_kms(display->drm,  in _panel_replay_init_dpcd()
618 	drm_dbg_kms(display->drm,  in _panel_replay_init_dpcd()
626 	struct intel_display *display = to_intel_display(intel_dp);  in _psr_init_dpcd()  local
628 	drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",  in _psr_init_dpcd()
632 		drm_dbg_kms(display->drm,  in _psr_init_dpcd()
638 		drm_dbg_kms(display->drm,  in _psr_init_dpcd()
647 	if (DISPLAY_VER(display) >= 9 &&  in _psr_init_dpcd()
665 		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",  in _psr_init_dpcd()
690 	struct intel_display *display = to_intel_display(intel_dp);  in hsw_psr_setup_aux()  local
691 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in hsw_psr_setup_aux()
707 			       psr_aux_data_reg(display, cpu_transcoder, i >> 2),  in hsw_psr_setup_aux()
722 	intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder),  in hsw_psr_setup_aux()
728 	struct intel_display *display = to_intel_display(intel_dp);  in psr2_su_region_et_valid()  local
730 	if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) ||  in psr2_su_region_et_valid()
769 	struct intel_display *display = to_intel_display(intel_dp);  in _psr_enable_sink()  local
778 		if (DISPLAY_VER(display) >= 8)  in _psr_enable_sink()
832 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr1_get_tp_time()  local
834 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_psr1_get_tp_time()
837 	if (DISPLAY_VER(display) >= 11)  in intel_psr1_get_tp_time()
840 	if (display->params.psr_safest_params) {  in intel_psr1_get_tp_time()
874 	if (intel_dp_source_supports_tps3(display) &&  in intel_psr1_get_tp_time()
885 	struct intel_display *display = to_intel_display(intel_dp);  in psr_compute_idle_frames()  local
895 	if (drm_WARN_ON(display->drm, idle_frames > 0xf))  in psr_compute_idle_frames()
903 	struct intel_display *display = to_intel_display(intel_dp);  in hsw_activate_psr1()  local
904 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in hsw_activate_psr1()
911 	if (DISPLAY_VER(display) < 20)  in hsw_activate_psr1()
922 	if (DISPLAY_VER(display) >= 8)  in hsw_activate_psr1()
925 	if (DISPLAY_VER(display) >= 20)  in hsw_activate_psr1()
928 	intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder),  in hsw_activate_psr1()
934 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr2_get_tp_time()  local
938 	if (display->params.psr_safest_params)  in intel_psr2_get_tp_time()
982 	struct intel_display *display = to_intel_display(intel_dp);  in dg2_activate_panel_replay()  local
993 		intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder),  in dg2_activate_panel_replay()
997 	intel_de_rmw(display,  in dg2_activate_panel_replay()
998 		     PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),  in dg2_activate_panel_replay()
1001 	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,  in dg2_activate_panel_replay()
1007 	struct intel_display *display = to_intel_display(intel_dp);  in hsw_activate_psr2()  local
1008 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in hsw_activate_psr2()
1015 	if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))  in hsw_activate_psr2()
1018 	if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13)  in hsw_activate_psr2()
1025 	if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) {  in hsw_activate_psr2()
1033 	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) {  in hsw_activate_psr2()
1056 	} else if (DISPLAY_VER(display) >= 20) {  in hsw_activate_psr2()
1058 	} else if (DISPLAY_VER(display) >= 12) {  in hsw_activate_psr2()
1061 	} else if (DISPLAY_VER(display) >= 9) {  in hsw_activate_psr2()
1069 	if (DISPLAY_VER(display) >= 20)  in hsw_activate_psr2()
1075 		tmp = intel_de_read(display,  in hsw_activate_psr2()
1076 				    PSR2_MAN_TRK_CTL(display, cpu_transcoder));  in hsw_activate_psr2()
1077 		drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));  in hsw_activate_psr2()
1078 	} else if (HAS_PSR2_SEL_FETCH(display)) {  in hsw_activate_psr2()
1079 		intel_de_write(display,  in hsw_activate_psr2()
1080 			       PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0);  in hsw_activate_psr2()
1090 	intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val);  in hsw_activate_psr2()
1092 	intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val);  in hsw_activate_psr2()
1096 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder)  in transcoder_has_psr2()  argument
1098 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in transcoder_has_psr2()
1100 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14)  in transcoder_has_psr2()
1102 	else if (DISPLAY_VER(display) >= 12)  in transcoder_has_psr2()
1104 	else if (DISPLAY_VER(display) >= 9)  in transcoder_has_psr2()
1122 	struct intel_display *display = to_intel_display(intel_dp);  in psr2_program_idle_frames()  local
1125 	intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder),  in psr2_program_idle_frames()
1132 	struct intel_display *display = to_intel_display(intel_dp);  in tgl_psr2_enable_dc3co()  local
1135 	intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);  in tgl_psr2_enable_dc3co()
1140 	struct intel_display *display = to_intel_display(intel_dp);  in tgl_psr2_disable_dc3co()  local
1142 	intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);  in tgl_psr2_disable_dc3co()
1175 	struct intel_display *display = to_intel_display(intel_dp);  in dc3co_is_pipe_port_compatible()  local
1178 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in dc3co_is_pipe_port_compatible()
1181 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14)  in dc3co_is_pipe_port_compatible()
1191 	struct intel_display *display = to_intel_display(intel_dp);  in tgl_dc3co_exitline_compute_config()  local
1192 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in tgl_dc3co_exitline_compute_config()
1194 	struct i915_power_domains *power_domains = &display->power.domains;  in tgl_dc3co_exitline_compute_config()
1218 	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))  in tgl_dc3co_exitline_compute_config()
1228 	if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))  in tgl_dc3co_exitline_compute_config()
1237 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr2_sel_fetch_config_valid()  local
1239 	if (!display->params.enable_psr2_sel_fetch &&  in intel_psr2_sel_fetch_config_valid()
1241 		drm_dbg_kms(display->drm,  in intel_psr2_sel_fetch_config_valid()
1247 		drm_dbg_kms(display->drm,  in intel_psr2_sel_fetch_config_valid()
1258 	struct intel_display *display = to_intel_display(intel_dp);  in psr2_granularity_check()  local
1259 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in psr2_granularity_check()
1281 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14)  in psr2_granularity_check()
1302 	struct intel_display *display = to_intel_display(intel_dp);  in _compute_psr2_sdp_prior_scanline_indication()  local
1316 	if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)  in _compute_psr2_sdp_prior_scanline_indication()
1326 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_entry_setup_frames()  local
1331 		drm_dbg_kms(display->drm,  in intel_psr_entry_setup_frames()
1339 		if (DISPLAY_VER(display) >= 20) {  in intel_psr_entry_setup_frames()
1342 			drm_dbg_kms(display->drm,  in intel_psr_entry_setup_frames()
1346 			drm_dbg_kms(display->drm,  in intel_psr_entry_setup_frames()
1360 	struct intel_display *display = to_intel_display(intel_dp);  in wake_lines_fit_into_vblank()  local
1368 		wake_lines = DISPLAY_VER(display) < 20 ?  in wake_lines_fit_into_vblank()
1386 	struct intel_display *display = to_intel_display(intel_dp);  in alpm_config_valid()  local
1389 		drm_dbg_kms(display->drm,  in alpm_config_valid()
1395 		drm_dbg_kms(display->drm,  in alpm_config_valid()
1406 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr2_config_valid()  local
1407 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_psr2_config_valid()
1417 		drm_dbg_kms(display->drm, "PSR2 not supported by phy\n");  in intel_psr2_config_valid()
1424 		drm_dbg_kms(display->drm,  in intel_psr2_config_valid()
1429 	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {  in intel_psr2_config_valid()
1430 		drm_dbg_kms(display->drm,  in intel_psr2_config_valid()
1435 	if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {  in intel_psr2_config_valid()
1436 		drm_dbg_kms(display->drm,  in intel_psr2_config_valid()
1448 	    (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))) {  in intel_psr2_config_valid()
1449 		drm_dbg_kms(display->drm,  in intel_psr2_config_valid()
1454 	if (DISPLAY_VER(display) >= 20) {  in intel_psr2_config_valid()
1458 	} else if (IS_DISPLAY_VER(display, 12, 14)) {  in intel_psr2_config_valid()
1462 	} else if (IS_DISPLAY_VER(display, 10, 11)) {  in intel_psr2_config_valid()
1466 	} else if (DISPLAY_VER(display) == 9) {  in intel_psr2_config_valid()
1473 		drm_dbg_kms(display->drm,  in intel_psr2_config_valid()
1481 	    IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {  in intel_psr2_config_valid()
1482 		drm_dbg_kms(display->drm,  in intel_psr2_config_valid()
1492 		drm_dbg_kms(display->drm,  in intel_psr2_config_valid()
1507 	struct intel_display *display = to_intel_display(intel_dp);  in intel_sel_update_config_valid()  local
1509 	if (HAS_PSR2_SEL_FETCH(display) &&  in intel_sel_update_config_valid()
1511 	    !HAS_PSR_HW_TRACKING(display)) {  in intel_sel_update_config_valid()
1512 		drm_dbg_kms(display->drm,  in intel_sel_update_config_valid()
1518 		drm_dbg_kms(display->drm,  in intel_sel_update_config_valid()
1527 		drm_dbg_kms(display->drm,  in intel_sel_update_config_valid()
1532 	if (crtc_state->has_panel_replay && (DISPLAY_VER(display) < 14 ||  in intel_sel_update_config_valid()
1537 		drm_dbg_kms(display->drm,  in intel_sel_update_config_valid()
1543 		drm_dbg_kms(display->drm,  in intel_sel_update_config_valid()
1561 	struct intel_display *display = to_intel_display(intel_dp);  in _psr_compute_config()  local
1573 		drm_dbg_kms(display->drm,  in _psr_compute_config()
1586 	struct intel_display *display = to_intel_display(intel_dp);  in _panel_replay_compute_config()  local
1595 		drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");  in _panel_replay_compute_config()
1610 		drm_dbg_kms(display->drm,  in _panel_replay_compute_config()
1621 		drm_dbg_kms(display->drm,  in _panel_replay_compute_config()
1630 		drm_dbg_kms(display->drm,  in _panel_replay_compute_config()
1641 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_needs_wa_18037818876()  local
1643 	return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 &&  in intel_psr_needs_wa_18037818876()
1651 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_compute_config()  local
1655 		drm_dbg_kms(display->drm, "PSR disabled by flag\n");  in intel_psr_compute_config()
1660 		drm_dbg_kms(display->drm,  in intel_psr_compute_config()
1666 		drm_dbg_kms(display->drm,  in intel_psr_compute_config()
1677 		drm_dbg_kms(display->drm,  in intel_psr_compute_config()
1703 		drm_dbg_kms(display->drm,  in intel_psr_compute_config()
1711 	struct intel_display *display = to_intel_display(encoder);  in intel_psr_get_config()  local
1744 	if (HAS_PSR2_SEL_FETCH(display)) {  in intel_psr_get_config()
1745 		val = intel_de_read(display,  in intel_psr_get_config()
1746 				    PSR2_MAN_TRK_CTL(display, cpu_transcoder));  in intel_psr_get_config()
1753 	if (DISPLAY_VER(display) >= 12) {  in intel_psr_get_config()
1754 		val = intel_de_read(display,  in intel_psr_get_config()
1755 				    TRANS_EXITLINE(display, cpu_transcoder));  in intel_psr_get_config()
1764 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_activate()  local
1767 	drm_WARN_ON(display->drm,  in intel_psr_activate()
1768 		    transcoder_has_psr2(display, cpu_transcoder) &&  in intel_psr_activate()
1769 		    intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE);  in intel_psr_activate()
1771 	drm_WARN_ON(display->drm,  in intel_psr_activate()
1772 		    intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE);  in intel_psr_activate()
1774 	drm_WARN_ON(display->drm, intel_dp->psr.active);  in intel_psr_activate()
1796 	struct intel_display *display = to_intel_display(intel_dp);  in wm_optimization_wa()  local
1801 	if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled)  in wm_optimization_wa()
1805 	if (DISPLAY_VER(display) == 12 &&  in wm_optimization_wa()
1811 		intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,  in wm_optimization_wa()
1814 		intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,  in wm_optimization_wa()
1821 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_enable_source()  local
1822 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_psr_enable_source()
1830 	if (DISPLAY_VER(display) < 9)  in intel_psr_enable_source()
1847 	if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp))  in intel_psr_enable_source()
1857 		 * higher than should be possible with an external display.  in intel_psr_enable_source()
1861 		if (DISPLAY_VER(display) >= 8 || IS_HASWELL_ULT(dev_priv))  in intel_psr_enable_source()
1864 		if (DISPLAY_VER(display) < 20)  in intel_psr_enable_source()
1871 		if (IS_DISPLAY_VER(display, 9, 10))  in intel_psr_enable_source()
1879 	intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask);  in intel_psr_enable_source()
1888 		intel_de_rmw(display,  in intel_psr_enable_source()
1889 			     TRANS_EXITLINE(display, cpu_transcoder),  in intel_psr_enable_source()
1893 	if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display))  in intel_psr_enable_source()
1894 		intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,  in intel_psr_enable_source()
1908 		if (DISPLAY_VER(display) == 9)  in intel_psr_enable_source()
1909 			intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0,  in intel_psr_enable_source()
1919 		    (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||  in intel_psr_enable_source()
1921 			intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),  in intel_psr_enable_source()
1926 		    IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))  in intel_psr_enable_source()
1927 			intel_de_rmw(display,  in intel_psr_enable_source()
1928 				     MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),  in intel_psr_enable_source()
1932 			intel_de_rmw(display, CLKGATE_DIS_MISC, 0,  in intel_psr_enable_source()
1939 	struct intel_display *display = to_intel_display(intel_dp);  in psr_interrupt_error_check()  local
1954 	val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));  in psr_interrupt_error_check()
1958 		drm_dbg_kms(display->drm,  in psr_interrupt_error_check()
1970 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_enable_locked()  local
1974 	drm_WARN_ON(display->drm, intel_dp->psr.enabled);  in intel_psr_enable_locked()
1995 		drm_dbg_kms(display->drm, "Enabling Panel Replay\n");  in intel_psr_enable_locked()
1997 		drm_dbg_kms(display->drm, "Enabling PSR%s\n",  in intel_psr_enable_locked()
2028 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_exit()  local
2033 		if (transcoder_has_psr2(display, cpu_transcoder)) {  in intel_psr_exit()
2034 			val = intel_de_read(display,  in intel_psr_exit()
2035 					    EDP_PSR2_CTL(display, cpu_transcoder));  in intel_psr_exit()
2036 			drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE);  in intel_psr_exit()
2039 		val = intel_de_read(display,  in intel_psr_exit()
2040 				    psr_ctl_reg(display, cpu_transcoder));  in intel_psr_exit()
2041 		drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE);  in intel_psr_exit()
2047 		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),  in intel_psr_exit()
2052 		val = intel_de_rmw(display,  in intel_psr_exit()
2053 				   EDP_PSR2_CTL(display, cpu_transcoder),  in intel_psr_exit()
2056 		drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE));  in intel_psr_exit()
2058 		val = intel_de_rmw(display,  in intel_psr_exit()
2059 				   psr_ctl_reg(display, cpu_transcoder),  in intel_psr_exit()
2062 		drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE));  in intel_psr_exit()
2069 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_wait_exit_locked()  local
2076 		psr_status = EDP_PSR2_STATUS(display, cpu_transcoder);  in intel_psr_wait_exit_locked()
2079 		psr_status = psr_status_reg(display, cpu_transcoder);  in intel_psr_wait_exit_locked()
2084 	if (intel_de_wait_for_clear(display, psr_status,  in intel_psr_wait_exit_locked()
2086 		drm_err(display->drm, "Timed out waiting PSR idle state\n");  in intel_psr_wait_exit_locked()
2091 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_disable_locked()  local
2092 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_psr_disable_locked()
2101 		drm_dbg_kms(display->drm, "Disabling Panel Replay\n");  in intel_psr_disable_locked()
2103 		drm_dbg_kms(display->drm, "Disabling PSR%s\n",  in intel_psr_disable_locked()
2113 	if (DISPLAY_VER(display) >= 11)  in intel_psr_disable_locked()
2114 		intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,  in intel_psr_disable_locked()
2120 		    IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))  in intel_psr_disable_locked()
2121 			intel_de_rmw(display,  in intel_psr_disable_locked()
2122 				     MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),  in intel_psr_disable_locked()
2125 			intel_de_rmw(display, CLKGATE_DIS_MISC,  in intel_psr_disable_locked()
2134 		intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder),  in intel_psr_disable_locked()
2138 		intel_de_rmw(display,  in intel_psr_disable_locked()
2170 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_disable()  local
2175 	if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp)))  in intel_psr_disable()
2197 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_pause()  local
2211 	drm_WARN_ON(display->drm, psr->paused);  in intel_psr_pause()
2278 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)  in man_trk_ctl_enable_bit_get()  argument
2280 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in man_trk_ctl_enable_bit_get()
2282 	return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? 0 :  in man_trk_ctl_enable_bit_get()
2286 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display)  in man_trk_ctl_single_full_frame_bit_get()  argument
2288 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in man_trk_ctl_single_full_frame_bit_get()
2290 	return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ?  in man_trk_ctl_single_full_frame_bit_get()
2295 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display)  in man_trk_ctl_partial_frame_bit_get()  argument
2297 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in man_trk_ctl_partial_frame_bit_get()
2299 	return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ?  in man_trk_ctl_partial_frame_bit_get()
2304 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display)  in man_trk_ctl_continuos_full_frame()  argument
2306 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in man_trk_ctl_continuos_full_frame()
2308 	return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ?  in man_trk_ctl_continuos_full_frame()
2315 	struct intel_display *display = to_intel_display(intel_dp);  in psr_force_hw_tracking_exit()  local
2319 		intel_de_write(display,  in psr_force_hw_tracking_exit()
2320 			       PSR2_MAN_TRK_CTL(display, cpu_transcoder),  in psr_force_hw_tracking_exit()
2321 			       man_trk_ctl_enable_bit_get(display) |  in psr_force_hw_tracking_exit()
2322 			       man_trk_ctl_partial_frame_bit_get(display) |  in psr_force_hw_tracking_exit()
2323 			       man_trk_ctl_single_full_frame_bit_get(display) |  in psr_force_hw_tracking_exit()
2324 			       man_trk_ctl_continuos_full_frame(display));  in psr_force_hw_tracking_exit()
2327 	 * Display WA #0884: skl+  in psr_force_hw_tracking_exit()
2335 	 * This workaround do not exist for platforms with display 10 or newer  in psr_force_hw_tracking_exit()
2336 	 * but testing proved that it works for up display 13, for newer  in psr_force_hw_tracking_exit()
2339 	intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);  in psr_force_hw_tracking_exit()
2344 	struct intel_display *display = to_intel_display(crtc_state);  in intel_psr2_program_trans_man_trk_ctl()  local
2352 	for_each_intel_encoder_mask_with_psr(display->drm, encoder,  in intel_psr2_program_trans_man_trk_ctl()
2362 	intel_de_write(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder),  in intel_psr2_program_trans_man_trk_ctl()
2368 	intel_de_write(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),  in intel_psr2_program_trans_man_trk_ctl()
2375 	struct intel_display *display = to_intel_display(crtc_state);  in psr2_man_trk_ctl_calc()  local
2378 	u32 val = man_trk_ctl_enable_bit_get(display);  in psr2_man_trk_ctl_calc()
2381 	val |= man_trk_ctl_partial_frame_bit_get(display);  in psr2_man_trk_ctl_calc()
2384 		val |= man_trk_ctl_single_full_frame_bit_get(display);  in psr2_man_trk_ctl_calc()
2385 		val |= man_trk_ctl_continuos_full_frame(display);  in psr2_man_trk_ctl_calc()
2392 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) {  in psr2_man_trk_ctl_calc()
2445 	struct intel_display *display = to_intel_display(crtc_state);  in intel_psr2_sel_fetch_pipe_alignment()  local
2452 	    (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14))  in intel_psr2_sel_fetch_pipe_alignment()
2540 	struct intel_display *display = to_intel_display(crtc_state);  in intel_psr_apply_pr_link_on_su_wa()  local
2556 	for_each_intel_encoder_mask_with_psr(display->drm, encoder,  in intel_psr_apply_pr_link_on_su_wa()
2572 	struct intel_display *display = to_intel_display(crtc_state);  in intel_psr_apply_su_area_workarounds()  local
2577 	    ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||  in intel_psr_apply_su_area_workarounds()
2583 	if (DISPLAY_VER(display) == 30)  in intel_psr_apply_su_area_workarounds()
2590 	struct intel_display *display = to_intel_display(state);  in intel_psr2_sel_fetch_update()  local
2686 		drm_info_once(display->drm,  in intel_psr2_sel_fetch_update()
2778 	struct intel_display *display = to_intel_display(state);  in intel_psr_pre_plane_update()  local
2786 	if (!HAS_PSR(display))  in intel_psr_pre_plane_update()
2803 		 * - Display WA #1136: skl, bxt  in intel_psr_pre_plane_update()
2827 	struct intel_display *display = to_intel_display(state);  in intel_psr_post_plane_update()  local
2843 		drm_WARN_ON(display->drm,  in intel_psr_post_plane_update()
2849 		/* Display WA #1136: skl, bxt */  in intel_psr_post_plane_update()
2850 		keep_disabled |= DISPLAY_VER(display) < 11 &&  in intel_psr_post_plane_update()
2875 	struct intel_display *display = to_intel_display(intel_dp);  in _psr2_ready_for_pipe_update_locked()  local
2883 	return intel_de_wait_for_clear(display,  in _psr2_ready_for_pipe_update_locked()
2884 				       EDP_PSR2_STATUS(display, cpu_transcoder),  in _psr2_ready_for_pipe_update_locked()
2890 	struct intel_display *display = to_intel_display(intel_dp);  in _psr1_ready_for_pipe_update_locked()  local
2899 	return intel_de_wait_for_clear(display,  in _psr1_ready_for_pipe_update_locked()
2900 				       psr_status_reg(display, cpu_transcoder),  in _psr1_ready_for_pipe_update_locked()
2913 	struct intel_display *display = to_intel_display(new_crtc_state);  in intel_psr_wait_for_idle_locked()  local
2919 	for_each_intel_encoder_mask_with_psr(display->drm, encoder,  in intel_psr_wait_for_idle_locked()
2935 			drm_err(display->drm,  in intel_psr_wait_for_idle_locked()
2942 	struct intel_display *display = to_intel_display(intel_dp);  in __psr_wait_for_idle_locked()  local
2953 		reg = EDP_PSR2_STATUS(display, cpu_transcoder);  in __psr_wait_for_idle_locked()
2956 		reg = psr_status_reg(display, cpu_transcoder);  in __psr_wait_for_idle_locked()
2962 	err = intel_de_wait_for_clear(display, reg, mask, 50);  in __psr_wait_for_idle_locked()
2964 		drm_err(display->drm,  in __psr_wait_for_idle_locked()
2972 static int intel_psr_fastset_force(struct intel_display *display)  in intel_psr_fastset_force()  argument
2980 	state = drm_atomic_state_alloc(display->drm);  in intel_psr_fastset_force()
2990 	drm_connector_list_iter_begin(display->drm, &conn_iter);  in intel_psr_fastset_force()
3037 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_debug_set()  local
3048 		drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val);  in intel_psr_debug_set()
3073 		ret = intel_psr_fastset_force(display);  in intel_psr_debug_set()
3125 	struct intel_display *display = to_intel_display(intel_dp);  in _psr_invalidate_handle()  local
3133 			intel_de_write(display,  in _psr_invalidate_handle()
3134 				       CURSURFLIVE(display, intel_dp->psr.pipe),  in _psr_invalidate_handle()
3139 		val = man_trk_ctl_enable_bit_get(display) |  in _psr_invalidate_handle()
3140 		      man_trk_ctl_partial_frame_bit_get(display) |  in _psr_invalidate_handle()
3141 		      man_trk_ctl_continuos_full_frame(display);  in _psr_invalidate_handle()
3142 		intel_de_write(display,  in _psr_invalidate_handle()
3143 			       PSR2_MAN_TRK_CTL(display, cpu_transcoder),  in _psr_invalidate_handle()
3145 		intel_de_write(display,  in _psr_invalidate_handle()
3146 			       CURSURFLIVE(display, intel_dp->psr.pipe), 0);  in _psr_invalidate_handle()
3155  * @display: display device
3166 void intel_psr_invalidate(struct intel_display *display,  in intel_psr_invalidate()  argument
3174 	for_each_intel_encoder_with_psr(display->drm, encoder) {  in intel_psr_invalidate()
3204 	struct intel_display *display = to_intel_display(intel_dp);  in tgl_dc3co_flush_locked()  local
3205 	struct drm_i915_private *i915 = to_i915(display->drm);  in tgl_dc3co_flush_locked()
3213 	 * when delayed work schedules that means display has been idle.  in tgl_dc3co_flush_locked()
3226 	struct intel_display *display = to_intel_display(intel_dp);  in _psr_flush_handle()  local
3227 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in _psr_flush_handle()
3234 				u32 val = man_trk_ctl_enable_bit_get(display) |  in _psr_flush_handle()
3235 					man_trk_ctl_partial_frame_bit_get(display) |  in _psr_flush_handle()
3236 					man_trk_ctl_single_full_frame_bit_get(display) |  in _psr_flush_handle()
3237 					man_trk_ctl_continuos_full_frame(display);  in _psr_flush_handle()
3245 				intel_de_write(display,  in _psr_flush_handle()
3246 					       PSR2_MAN_TRK_CTL(display, cpu_transcoder),  in _psr_flush_handle()
3248 				intel_de_write(display,  in _psr_flush_handle()
3249 					       CURSURFLIVE(display, intel_dp->psr.pipe),  in _psr_flush_handle()
3270  * @display: display device
3281 void intel_psr_flush(struct intel_display *display,  in intel_psr_flush()  argument
3286 	for_each_intel_encoder_with_psr(display->drm, encoder) {  in intel_psr_flush()
3335 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_init()  local
3339 	if (!(HAS_PSR(display) || HAS_DP20(display)))  in intel_psr_init()
3351 	if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) {  in intel_psr_init()
3352 		drm_dbg_kms(display->drm,  in intel_psr_init()
3357 	if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) ||  in intel_psr_init()
3358 	    DISPLAY_VER(display) >= 20)  in intel_psr_init()
3361 	if (HAS_PSR(display) && intel_dp_is_edp(intel_dp))  in intel_psr_init()
3365 	if (DISPLAY_VER(display) < 12)  in intel_psr_init()
3402 	struct intel_display *display = to_intel_display(intel_dp);  in psr_alpm_check()  local
3413 		drm_err(display->drm, "Error reading ALPM status\n");  in psr_alpm_check()
3420 		drm_dbg_kms(display->drm,  in psr_alpm_check()
3430 	struct intel_display *display = to_intel_display(intel_dp);  in psr_capability_changed_check()  local
3437 		drm_err(display->drm, "Error reading DP_PSR_ESI\n");  in psr_capability_changed_check()
3444 		drm_dbg_kms(display->drm,  in psr_capability_changed_check()
3461 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_short_pulse()  local
3479 		drm_err(display->drm,  in intel_psr_short_pulse()
3492 		drm_dbg_kms(display->drm,  in intel_psr_short_pulse()
3495 		drm_dbg_kms(display->drm,  in intel_psr_short_pulse()
3498 		drm_dbg_kms(display->drm,  in intel_psr_short_pulse()
3501 		drm_dbg_kms(display->drm,  in intel_psr_short_pulse()
3505 		drm_err(display->drm,  in intel_psr_short_pulse()
3571 	struct intel_display *display = to_intel_display(crtc_state);  in intel_psr_lock()  local
3577 	for_each_intel_encoder_mask_with_psr(display->drm, encoder,  in intel_psr_lock()
3594 	struct intel_display *display = to_intel_display(crtc_state);  in intel_psr_unlock()  local
3600 	for_each_intel_encoder_mask_with_psr(display->drm, encoder,  in intel_psr_unlock()
3612 	struct intel_display *display = to_intel_display(intel_dp);  in psr_source_status()  local
3632 		val = intel_de_read(display,  in psr_source_status()
3633 				    EDP_PSR2_STATUS(display, cpu_transcoder));  in psr_source_status()
3648 		val = intel_de_read(display,  in psr_source_status()
3649 				    psr_status_reg(display, cpu_transcoder));  in psr_source_status()
3710 	struct intel_display *display = to_intel_display(intel_dp);  in intel_psr_status()  local
3711 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_psr_status()
3736 		val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));  in intel_psr_status()
3739 			psr2_ctl = intel_de_read(display,  in intel_psr_status()
3740 						 EDP_PSR2_CTL(display,  in intel_psr_status()
3745 		val = intel_de_read(display,  in intel_psr_status()
3746 				    EDP_PSR2_CTL(display, cpu_transcoder));  in intel_psr_status()
3749 		val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));  in intel_psr_status()
3764 	val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));  in intel_psr_status()
3783 			val = intel_de_read(display,  in intel_psr_status()
3784 					    PSR2_SU_STATUS(display, cpu_transcoder, frame));  in intel_psr_status()
3812 	struct intel_display *display = m->private;  in i915_edp_psr_status_show()  local
3816 	if (!HAS_PSR(display))  in i915_edp_psr_status_show()
3820 	for_each_intel_encoder_with_psr(display->drm, encoder) {  in i915_edp_psr_status_show()
3835 	struct intel_display *display = data;  in i915_edp_psr_debug_set()  local
3836 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in i915_edp_psr_debug_set()
3841 	if (!HAS_PSR(display))  in i915_edp_psr_debug_set()
3844 	for_each_intel_encoder_with_psr(display->drm, encoder) {  in i915_edp_psr_debug_set()
3847 		drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val);  in i915_edp_psr_debug_set()
3863 	struct intel_display *display = data;  in i915_edp_psr_debug_get()  local
3866 	if (!HAS_PSR(display))  in i915_edp_psr_debug_get()
3869 	for_each_intel_encoder_with_psr(display->drm, encoder) {  in i915_edp_psr_debug_get()
3884 void intel_psr_debugfs_register(struct intel_display *display)  in intel_psr_debugfs_register()  argument
3886 	struct drm_minor *minor = display->drm->primary;  in intel_psr_debugfs_register()
3889 			    display, &i915_edp_psr_debug_fops);  in intel_psr_debugfs_register()
3892 			    display, &i915_edp_psr_status_fops);  in intel_psr_debugfs_register()
3911 		"transition to active, capture and display",  in i915_psr_sink_status_show()
3912 		"active, display from RFB",  in i915_psr_sink_status_show()
3913 		"active, capture and display on sink device timings",  in i915_psr_sink_status_show()
3914 		"transition to inactive, capture and display, timing re-sync",  in i915_psr_sink_status_show()
3973 	struct intel_display *display = to_intel_display(connector);  in intel_psr_connector_debugfs_add()  local
3983 	if (HAS_PSR(display) || HAS_DP20(display))  in intel_psr_connector_debugfs_add()