19 	struct intel_display *display = to_intel_display(connector);  in intel_vrr_is_capable()  local
45 	return HAS_VRR(display) &&  in intel_vrr_is_capable()
96 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vrr_vblank_exit_length()  local
98 	if (DISPLAY_VER(display) >= 13)  in intel_vrr_vblank_exit_length()
119 	struct intel_display *display = to_intel_display(crtc_state);  in is_cmrr_frac_required()  local
123 	if (!HAS_CMRR(display))  in is_cmrr_frac_required()
167 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vrr_compute_config()  local
191 	if (HAS_LRR(display))  in intel_vrr_compute_config()
250 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vrr_compute_config_late()  local
256 	if (DISPLAY_VER(display) >= 13) {  in intel_vrr_compute_config_late()
268 	struct intel_display *display = to_intel_display(crtc_state);  in trans_vrr_ctl()  local
270 	if (DISPLAY_VER(display) >= 13)  in trans_vrr_ctl()
281 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vrr_set_transcoder_timings()  local
289 	if (IS_DISPLAY_VER(display, 12, 13))  in intel_vrr_set_transcoder_timings()
290 		intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
294 		intel_de_write(display,  in intel_vrr_set_transcoder_timings()
295 			       TRANS_VRR_CTL(display, cpu_transcoder), 0);  in intel_vrr_set_transcoder_timings()
300 		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
302 		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
304 		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
306 		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
310 	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
312 	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
314 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
316 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),  in intel_vrr_set_transcoder_timings()
322 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vrr_send_push()  local
328 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),  in intel_vrr_send_push()
334 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vrr_is_push_sent()  local
340 	return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;  in intel_vrr_is_push_sent()
345 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vrr_enable()  local
351 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),  in intel_vrr_enable()
354 	if (HAS_AS_SDP(display))  in intel_vrr_enable()
355 		intel_de_write(display,  in intel_vrr_enable()
356 			       TRANS_VRR_VSYNC(display, cpu_transcoder),  in intel_vrr_enable()
361 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),  in intel_vrr_enable()
365 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),  in intel_vrr_enable()
372 	struct intel_display *display = to_intel_display(old_crtc_state);  in intel_vrr_disable()  local
378 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),  in intel_vrr_disable()
380 	intel_de_wait_for_clear(display,  in intel_vrr_disable()
381 				TRANS_VRR_STATUS(display, cpu_transcoder),  in intel_vrr_disable()
383 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);  in intel_vrr_disable()
385 	if (HAS_AS_SDP(display))  in intel_vrr_disable()
386 		intel_de_write(display,  in intel_vrr_disable()
387 			       TRANS_VRR_VSYNC(display, cpu_transcoder), 0);  in intel_vrr_disable()
392 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vrr_get_config()  local
396 	trans_vrr_ctl = intel_de_read(display,  in intel_vrr_get_config()
397 				      TRANS_VRR_CTL(display, cpu_transcoder));  in intel_vrr_get_config()
400 	if (HAS_CMRR(display))  in intel_vrr_get_config()
405 			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),  in intel_vrr_get_config()
406 					     TRANS_CMRR_N_HI(display, cpu_transcoder));  in intel_vrr_get_config()
408 			intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),  in intel_vrr_get_config()
409 					     TRANS_CMRR_M_HI(display, cpu_transcoder));  in intel_vrr_get_config()
412 	if (DISPLAY_VER(display) >= 13)  in intel_vrr_get_config()
421 		crtc_state->vrr.flipline = intel_de_read(display,  in intel_vrr_get_config()
422 							 TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;  in intel_vrr_get_config()
423 		crtc_state->vrr.vmax = intel_de_read(display,  in intel_vrr_get_config()
424 						     TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;  in intel_vrr_get_config()
425 		crtc_state->vrr.vmin = intel_de_read(display,  in intel_vrr_get_config()
426 						     TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;  in intel_vrr_get_config()
432 		if (HAS_AS_SDP(display)) {  in intel_vrr_get_config()
434 				intel_de_read(display,  in intel_vrr_get_config()
435 					      TRANS_VRR_VSYNC(display, cpu_transcoder));  in intel_vrr_get_config()