Lines Matching full:engine
36 static void set_hwstam(struct intel_engine_cs *engine, u32 mask) in set_hwstam() argument
42 if (engine->class == RENDER_CLASS) { in set_hwstam()
43 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
49 intel_engine_set_hwsp_writemask(engine, mask); in set_hwstam()
52 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) in set_hws_pga() argument
57 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
60 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
63 static struct page *status_page(struct intel_engine_cs *engine) in status_page() argument
65 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
71 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) in ring_setup_phys_status_page() argument
73 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); in ring_setup_phys_status_page()
74 set_hwstam(engine, ~0u); in ring_setup_phys_status_page()
77 static void set_hwsp(struct intel_engine_cs *engine, u32 offset) in set_hwsp() argument
85 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
86 switch (engine->id) { in set_hwsp()
92 GEM_BUG_ON(engine->id); in set_hwsp()
107 } else if (GRAPHICS_VER(engine->i915) == 6) { in set_hwsp()
108 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); in set_hwsp()
110 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
113 intel_uncore_write_fw(engine->uncore, hwsp, offset); in set_hwsp()
114 intel_uncore_posting_read_fw(engine->uncore, hwsp); in set_hwsp()
117 static void flush_cs_tlb(struct intel_engine_cs *engine) in flush_cs_tlb() argument
119 if (!IS_GRAPHICS_VER(engine->i915, 6, 7)) in flush_cs_tlb()
123 if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0) in flush_cs_tlb()
124 drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n", in flush_cs_tlb()
125 engine->name); in flush_cs_tlb()
127 ENGINE_WRITE_FW(engine, RING_INSTPM, in flush_cs_tlb()
130 if (__intel_wait_for_register_fw(engine->uncore, in flush_cs_tlb()
131 RING_INSTPM(engine->mmio_base), in flush_cs_tlb()
134 ENGINE_TRACE(engine, in flush_cs_tlb()
138 static void ring_setup_status_page(struct intel_engine_cs *engine) in ring_setup_status_page() argument
140 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
141 set_hwstam(engine, ~0u); in ring_setup_status_page()
143 flush_cs_tlb(engine); in ring_setup_status_page()
159 static void set_pp_dir(struct intel_engine_cs *engine) in set_pp_dir() argument
161 struct i915_address_space *vm = vm_alias(engine->gt->vm); in set_pp_dir()
166 ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G); in set_pp_dir()
167 ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm)); in set_pp_dir()
169 if (GRAPHICS_VER(engine->i915) >= 7) { in set_pp_dir()
170 ENGINE_WRITE_FW(engine, in set_pp_dir()
176 static bool stop_ring(struct intel_engine_cs *engine) in stop_ring() argument
179 ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL)); in stop_ring()
180 ENGINE_POSTING_READ(engine, RING_HEAD); in stop_ring()
183 ENGINE_WRITE_FW(engine, RING_CTL, 0); in stop_ring()
184 ENGINE_POSTING_READ(engine, RING_CTL); in stop_ring()
187 ENGINE_WRITE_FW(engine, RING_HEAD, 0); in stop_ring()
188 ENGINE_WRITE_FW(engine, RING_TAIL, 0); in stop_ring()
190 return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0; in stop_ring()
193 static int xcs_resume(struct intel_engine_cs *engine) in xcs_resume() argument
195 struct intel_ring *ring = engine->legacy.ring; in xcs_resume()
198 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n", in xcs_resume()
205 intel_synchronize_hardirq(engine->i915); in xcs_resume()
206 if (!stop_ring(engine)) in xcs_resume()
209 if (HWS_NEEDS_PHYSICAL(engine->i915)) in xcs_resume()
210 ring_setup_phys_status_page(engine); in xcs_resume()
212 ring_setup_status_page(engine); in xcs_resume()
214 intel_breadcrumbs_reset(engine->breadcrumbs); in xcs_resume()
217 ENGINE_POSTING_READ(engine, RING_HEAD); in xcs_resume()
225 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
232 set_pp_dir(engine); in xcs_resume()
236 * Use 50ms of delay to let the engine write successfully in xcs_resume()
243 * In case of resets fails because engine resumes from in xcs_resume()
248 ENGINE_WRITE_FW(engine, RING_HEAD, ring->head); in xcs_resume()
249 if (ENGINE_READ_FW(engine, RING_HEAD) == ring->head) in xcs_resume()
253 ENGINE_WRITE_FW(engine, RING_TAIL, ring->head); in xcs_resume()
254 if (ENGINE_READ_FW(engine, RING_HEAD) != ENGINE_READ_FW(engine, RING_TAIL)) { in xcs_resume()
255 ENGINE_TRACE(engine, "failed to reset empty ring: [%x, %x]: %x\n", in xcs_resume()
256 ENGINE_READ_FW(engine, RING_HEAD), in xcs_resume()
257 ENGINE_READ_FW(engine, RING_TAIL), in xcs_resume()
262 ENGINE_WRITE_FW(engine, RING_CTL, in xcs_resume()
266 if (__intel_wait_for_register_fw(engine->uncore, in xcs_resume()
267 RING_CTL(engine->mmio_base), in xcs_resume()
270 ENGINE_TRACE(engine, "failed to restart\n"); in xcs_resume()
274 if (GRAPHICS_VER(engine->i915) > 2) { in xcs_resume()
275 ENGINE_WRITE_FW(engine, in xcs_resume()
277 ENGINE_POSTING_READ(engine, RING_MI_MODE); in xcs_resume()
282 ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail); in xcs_resume()
283 ENGINE_POSTING_READ(engine, RING_TAIL); in xcs_resume()
287 intel_engine_signal_breadcrumbs(engine); in xcs_resume()
291 gt_err(engine->gt, "%s initialization failed\n", engine->name); in xcs_resume()
292 ENGINE_TRACE(engine, in xcs_resume()
294 ENGINE_READ(engine, RING_CTL), in xcs_resume()
295 ENGINE_READ(engine, RING_CTL) & RING_VALID, in xcs_resume()
296 ENGINE_READ(engine, RING_HEAD), ring->head, in xcs_resume()
297 ENGINE_READ(engine, RING_TAIL), ring->tail, in xcs_resume()
298 ENGINE_READ(engine, RING_START), in xcs_resume()
304 static void sanitize_hwsp(struct intel_engine_cs *engine) in sanitize_hwsp() argument
308 list_for_each_entry(tl, &engine->status_page.timelines, engine_link) in sanitize_hwsp()
312 static void xcs_sanitize(struct intel_engine_cs *engine) in xcs_sanitize() argument
324 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE); in xcs_sanitize()
331 sanitize_hwsp(engine); in xcs_sanitize()
334 drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE); in xcs_sanitize()
336 intel_engine_reset_pinned_contexts(engine); in xcs_sanitize()
339 static void reset_prepare(struct intel_engine_cs *engine) in reset_prepare() argument
356 ENGINE_TRACE(engine, "\n"); in reset_prepare()
357 intel_engine_stop_cs(engine); in reset_prepare()
359 if (!stop_ring(engine)) { in reset_prepare()
361 ENGINE_TRACE(engine, in reset_prepare()
364 ENGINE_READ_FW(engine, RING_CTL), in reset_prepare()
365 ENGINE_READ_FW(engine, RING_HEAD), in reset_prepare()
366 ENGINE_READ_FW(engine, RING_TAIL), in reset_prepare()
367 ENGINE_READ_FW(engine, RING_START)); in reset_prepare()
368 if (!stop_ring(engine)) { in reset_prepare()
369 drm_err(&engine->i915->drm, in reset_prepare()
372 engine->name, in reset_prepare()
373 ENGINE_READ_FW(engine, RING_CTL), in reset_prepare()
374 ENGINE_READ_FW(engine, RING_HEAD), in reset_prepare()
375 ENGINE_READ_FW(engine, RING_TAIL), in reset_prepare()
376 ENGINE_READ_FW(engine, RING_START)); in reset_prepare()
381 static void reset_rewind(struct intel_engine_cs *engine, bool stalled) in reset_rewind() argument
388 spin_lock_irqsave(&engine->sched_engine->lock, flags); in reset_rewind()
390 list_for_each_entry(pos, &engine->sched_engine->requests, sched.link) { in reset_rewind()
399 * The guilty request will get skipped on a hung engine. in reset_rewind()
438 GEM_BUG_ON(rq->ring != engine->legacy.ring); in reset_rewind()
441 head = engine->legacy.ring->tail; in reset_rewind()
443 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); in reset_rewind()
445 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); in reset_rewind()
448 static void reset_finish(struct intel_engine_cs *engine) in reset_finish() argument
452 static void reset_cancel(struct intel_engine_cs *engine) in reset_cancel() argument
457 spin_lock_irqsave(&engine->sched_engine->lock, flags); in reset_cancel()
460 list_for_each_entry(request, &engine->sched_engine->requests, sched.link) in reset_cancel()
462 intel_engine_signal_breadcrumbs(engine); in reset_cancel()
466 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); in reset_cancel()
474 ENGINE_WRITE(request->engine, RING_TAIL, in i9xx_submit_request()
506 shmem_read(ce->default_state, 0, vaddr, ce->engine->context_size); in ring_context_init_default_state()
555 alloc_context_vma(struct intel_engine_cs *engine) in alloc_context_vma() argument
557 struct drm_i915_private *i915 = engine->i915; in alloc_context_vma()
562 obj = i915_gem_object_create_shmem(i915, engine->context_size); in alloc_context_vma()
584 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in alloc_context_vma()
599 struct intel_engine_cs *engine = ce->engine; in ring_context_alloc() local
602 ce->default_state = engine->default_state; in ring_context_alloc()
605 GEM_BUG_ON(!engine->legacy.ring); in ring_context_alloc()
606 ce->ring = engine->legacy.ring; in ring_context_alloc()
607 ce->timeline = intel_timeline_get(engine->legacy.timeline); in ring_context_alloc()
610 if (engine->context_size) { in ring_context_alloc()
613 vma = alloc_context_vma(engine); in ring_context_alloc()
638 struct intel_engine_cs *engine; in ring_context_revoke() local
643 engine = rq->engine; in ring_context_revoke()
644 lockdep_assert_held(&engine->sched_engine->lock); in ring_context_revoke()
645 list_for_each_entry_continue(rq, &engine->sched_engine->requests, in ring_context_revoke()
656 struct intel_engine_cs *engine = NULL; in ring_context_cancel_request() local
658 i915_request_active_engine(rq, &engine); in ring_context_cancel_request()
660 if (engine && intel_engine_pulse(engine)) in ring_context_cancel_request()
661 intel_gt_handle_error(engine->gt, engine->mask, 0, in ring_context_cancel_request()
689 const struct intel_engine_cs * const engine = rq->engine; in load_pd_dir() local
697 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
701 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
706 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
707 *cs++ = intel_gt_scratch_offset(engine->gt, in load_pd_dir()
711 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
716 return rq->engine->emit_flush(rq, EMIT_FLUSH); in load_pd_dir()
723 struct intel_engine_cs *engine = rq->engine; in mi_set_context() local
724 struct drm_i915_private *i915 = engine->i915; in mi_set_context()
727 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; in mi_set_context()
755 for_each_engine(signaller, engine->gt, id) { in mi_set_context()
756 if (signaller == engine) in mi_set_context()
789 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
809 for_each_engine(signaller, engine->gt, id) { in mi_set_context()
810 if (signaller == engine) in mi_set_context()
822 *cs++ = intel_gt_scratch_offset(engine->gt, in mi_set_context()
894 ret = rq->engine->emit_flush(rq, EMIT_FLUSH); in switch_mm()
910 return rq->engine->emit_flush(rq, EMIT_INVALIDATE); in switch_mm()
915 struct intel_engine_cs *engine = rq->engine; in clear_residuals() local
918 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm)); in clear_residuals()
922 if (engine->kernel_context->state) { in clear_residuals()
924 engine->kernel_context, in clear_residuals()
930 ret = engine->emit_bb_start(rq, in clear_residuals()
931 i915_vma_offset(engine->wa_ctx.vma), 0, in clear_residuals()
936 ret = engine->emit_flush(rq, EMIT_FLUSH); in clear_residuals()
941 return engine->emit_flush(rq, EMIT_INVALIDATE); in clear_residuals()
946 struct intel_engine_cs *engine = rq->engine; in switch_context() local
951 GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); in switch_context()
953 if (engine->wa_ctx.vma && ce != engine->kernel_context) { in switch_context()
954 if (engine->wa_ctx.vma->private != ce && in switch_context()
960 residuals = &engine->wa_ctx.vma->private; in switch_context()
971 GEM_BUG_ON(engine->id != RCS0); in switch_context()
1024 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); in ring_request_alloc()
1038 struct intel_uncore *uncore = request->engine->uncore; in gen6_bsd_submit_request()
1074 static void i9xx_set_default_submission(struct intel_engine_cs *engine) in i9xx_set_default_submission() argument
1076 engine->submit_request = i9xx_submit_request; in i9xx_set_default_submission()
1079 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) in gen6_bsd_set_default_submission() argument
1081 engine->submit_request = gen6_bsd_submit_request; in gen6_bsd_set_default_submission()
1084 static void ring_release(struct intel_engine_cs *engine) in ring_release() argument
1086 struct drm_i915_private *i915 = engine->i915; in ring_release()
1089 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); in ring_release()
1091 intel_engine_cleanup_common(engine); in ring_release()
1093 if (engine->wa_ctx.vma) { in ring_release()
1094 intel_context_put(engine->wa_ctx.vma->private); in ring_release()
1095 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); in ring_release()
1098 intel_ring_unpin(engine->legacy.ring); in ring_release()
1099 intel_ring_put(engine->legacy.ring); in ring_release()
1101 intel_timeline_unpin(engine->legacy.timeline); in ring_release()
1102 intel_timeline_put(engine->legacy.timeline); in ring_release()
1105 static void irq_handler(struct intel_engine_cs *engine, u16 iir) in irq_handler() argument
1107 intel_engine_signal_breadcrumbs(engine); in irq_handler()
1110 static void setup_irq(struct intel_engine_cs *engine) in setup_irq() argument
1112 struct drm_i915_private *i915 = engine->i915; in setup_irq()
1114 intel_engine_set_irq_handler(engine, irq_handler); in setup_irq()
1117 engine->irq_enable = gen6_irq_enable; in setup_irq()
1118 engine->irq_disable = gen6_irq_disable; in setup_irq()
1120 engine->irq_enable = gen5_irq_enable; in setup_irq()
1121 engine->irq_disable = gen5_irq_disable; in setup_irq()
1123 engine->irq_enable = gen2_irq_enable; in setup_irq()
1124 engine->irq_disable = gen2_irq_disable; in setup_irq()
1130 lockdep_assert_held(&rq->engine->sched_engine->lock); in add_to_engine()
1131 list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests); in add_to_engine()
1136 spin_lock_irq(&rq->engine->sched_engine->lock); in remove_from_engine()
1142 spin_unlock_irq(&rq->engine->sched_engine->lock); in remove_from_engine()
1147 static void setup_common(struct intel_engine_cs *engine) in setup_common() argument
1149 struct drm_i915_private *i915 = engine->i915; in setup_common()
1154 setup_irq(engine); in setup_common()
1156 engine->resume = xcs_resume; in setup_common()
1157 engine->sanitize = xcs_sanitize; in setup_common()
1159 engine->reset.prepare = reset_prepare; in setup_common()
1160 engine->reset.rewind = reset_rewind; in setup_common()
1161 engine->reset.cancel = reset_cancel; in setup_common()
1162 engine->reset.finish = reset_finish; in setup_common()
1164 engine->add_active_request = add_to_engine; in setup_common()
1165 engine->remove_active_request = remove_from_engine; in setup_common()
1167 engine->cops = &ring_context_ops; in setup_common()
1168 engine->request_alloc = ring_request_alloc; in setup_common()
1173 * engine->emit_init_breadcrumb(). in setup_common()
1175 engine->emit_fini_breadcrumb = gen2_emit_breadcrumb; in setup_common()
1177 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; in setup_common()
1179 engine->set_default_submission = i9xx_set_default_submission; in setup_common()
1182 engine->emit_bb_start = gen6_emit_bb_start; in setup_common()
1184 engine->emit_bb_start = gen4_emit_bb_start; in setup_common()
1186 engine->emit_bb_start = i830_emit_bb_start; in setup_common()
1188 engine->emit_bb_start = gen2_emit_bb_start; in setup_common()
1191 static void setup_rcs(struct intel_engine_cs *engine) in setup_rcs() argument
1193 struct drm_i915_private *i915 = engine->i915; in setup_rcs()
1196 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; in setup_rcs()
1198 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; in setup_rcs()
1201 engine->emit_flush = gen7_emit_flush_rcs; in setup_rcs()
1202 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; in setup_rcs()
1204 engine->emit_flush = gen6_emit_flush_rcs; in setup_rcs()
1205 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; in setup_rcs()
1207 engine->emit_flush = gen4_emit_flush_rcs; in setup_rcs()
1210 engine->emit_flush = gen2_emit_flush; in setup_rcs()
1212 engine->emit_flush = gen4_emit_flush_rcs; in setup_rcs()
1213 engine->irq_enable_mask = I915_USER_INTERRUPT; in setup_rcs()
1217 engine->emit_bb_start = hsw_emit_bb_start; in setup_rcs()
1220 static void setup_vcs(struct intel_engine_cs *engine) in setup_vcs() argument
1222 struct drm_i915_private *i915 = engine->i915; in setup_vcs()
1227 engine->set_default_submission = gen6_bsd_set_default_submission; in setup_vcs()
1228 engine->emit_flush = gen6_emit_flush_vcs; in setup_vcs()
1229 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; in setup_vcs()
1232 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; in setup_vcs()
1234 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_vcs()
1236 engine->emit_flush = gen4_emit_flush_vcs; in setup_vcs()
1238 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; in setup_vcs()
1240 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; in setup_vcs()
1244 static void setup_bcs(struct intel_engine_cs *engine) in setup_bcs() argument
1246 struct drm_i915_private *i915 = engine->i915; in setup_bcs()
1248 engine->emit_flush = gen6_emit_flush_xcs; in setup_bcs()
1249 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; in setup_bcs()
1252 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; in setup_bcs()
1254 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_bcs()
1257 static void setup_vecs(struct intel_engine_cs *engine) in setup_vecs() argument
1259 struct drm_i915_private *i915 = engine->i915; in setup_vecs()
1263 engine->emit_flush = gen6_emit_flush_xcs; in setup_vecs()
1264 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; in setup_vecs()
1265 engine->irq_enable = hsw_irq_enable_vecs; in setup_vecs()
1266 engine->irq_disable = hsw_irq_disable_vecs; in setup_vecs()
1268 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_vecs()
1271 static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine, in gen7_ctx_switch_bb_setup() argument
1274 return gen7_setup_clear_gpr_bb(engine, vma); in gen7_ctx_switch_bb_setup()
1277 static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine, in gen7_ctx_switch_bb_init() argument
1291 err = gen7_ctx_switch_bb_setup(engine, vma); in gen7_ctx_switch_bb_init()
1295 engine->wa_ctx.vma = vma; in gen7_ctx_switch_bb_init()
1303 static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine) in gen7_ctx_vma() argument
1309 if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS) in gen7_ctx_vma()
1312 err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */); in gen7_ctx_vma()
1320 obj = i915_gem_object_create_internal(engine->i915, size); in gen7_ctx_vma()
1324 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in gen7_ctx_vma()
1330 vma->private = intel_context_create(engine); /* dummy residuals */ in gen7_ctx_vma()
1341 int intel_ring_submission_setup(struct intel_engine_cs *engine) in intel_ring_submission_setup() argument
1349 setup_common(engine); in intel_ring_submission_setup()
1351 switch (engine->class) { in intel_ring_submission_setup()
1353 setup_rcs(engine); in intel_ring_submission_setup()
1356 setup_vcs(engine); in intel_ring_submission_setup()
1359 setup_bcs(engine); in intel_ring_submission_setup()
1362 setup_vecs(engine); in intel_ring_submission_setup()
1365 MISSING_CASE(engine->class); in intel_ring_submission_setup()
1369 timeline = intel_timeline_create_from_engine(engine, in intel_ring_submission_setup()
1377 ring = intel_engine_create_ring(engine, SZ_16K); in intel_ring_submission_setup()
1383 GEM_BUG_ON(engine->legacy.ring); in intel_ring_submission_setup()
1384 engine->legacy.ring = ring; in intel_ring_submission_setup()
1385 engine->legacy.timeline = timeline; in intel_ring_submission_setup()
1387 gen7_wa_vma = gen7_ctx_vma(engine); in intel_ring_submission_setup()
1400 err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww); in intel_ring_submission_setup()
1411 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); in intel_ring_submission_setup()
1414 err = gen7_ctx_switch_bb_init(engine, &ww, gen7_wa_vma); in intel_ring_submission_setup()
1432 engine->release = ring_release; in intel_ring_submission_setup()
1446 intel_engine_cleanup_common(engine); in intel_ring_submission_setup()