Lines Matching +full:lpddr4 +full:- +full:channel
1 // SPDX-License-Identifier: MIT
35 DRAM_TYPE_STR(LPDDR4), in intel_dram_type_str()
48 return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3; in pnv_is_ddr3()
55 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); in pnv_mem_freq()
73 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); in ilk_mem_freq()
84 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", in ilk_mem_freq()
130 i915->mem_freq = pnv_mem_freq(i915); in detect_mem_freq()
132 i915->mem_freq = ilk_mem_freq(i915); in detect_mem_freq()
134 i915->mem_freq = chv_mem_freq(i915); in detect_mem_freq()
136 i915->mem_freq = vlv_mem_freq(i915); in detect_mem_freq()
139 i915->is_ddr3 = pnv_is_ddr3(i915); in detect_mem_freq()
141 if (i915->mem_freq) in detect_mem_freq()
142 drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq); in detect_mem_freq()
157 fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; in i9xx_fsb_freq()
204 fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff; in ilk_fsb_freq()
222 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb); in ilk_fsb_freq()
230 i915->fsb_freq = ilk_fsb_freq(i915); in detect_fsb_freq()
232 i915->fsb_freq = i9xx_fsb_freq(i915); in detect_fsb_freq()
234 if (i915->fsb_freq) in detect_fsb_freq()
235 drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq); in detect_fsb_freq()
240 return dimm->ranks * 64 / (dimm->width ?: 1); in intel_dimm_num_devices()
313 return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16; in skl_is_16gb_dimm()
319 int channel, char dimm_name, u16 val) in skl_dram_get_dimm_info() argument
322 dimm->size = icl_get_dimm_size(val); in skl_dram_get_dimm_info()
323 dimm->width = icl_get_dimm_width(val); in skl_dram_get_dimm_info()
324 dimm->ranks = icl_get_dimm_ranks(val); in skl_dram_get_dimm_info()
326 dimm->size = skl_get_dimm_size(val); in skl_dram_get_dimm_info()
327 dimm->width = skl_get_dimm_width(val); in skl_dram_get_dimm_info()
328 dimm->ranks = skl_get_dimm_ranks(val); in skl_dram_get_dimm_info()
331 drm_dbg_kms(&i915->drm, in skl_dram_get_dimm_info()
333 channel, dimm_name, dimm->size, dimm->width, dimm->ranks, in skl_dram_get_dimm_info()
340 int channel, u32 val) in skl_dram_get_channel_info() argument
342 skl_dram_get_dimm_info(i915, &ch->dimm_l, in skl_dram_get_channel_info()
343 channel, 'L', val & 0xffff); in skl_dram_get_channel_info()
344 skl_dram_get_dimm_info(i915, &ch->dimm_s, in skl_dram_get_channel_info()
345 channel, 'S', val >> 16); in skl_dram_get_channel_info()
347 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) { in skl_dram_get_channel_info()
348 drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel); in skl_dram_get_channel_info()
349 return -EINVAL; in skl_dram_get_channel_info()
352 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2) in skl_dram_get_channel_info()
353 ch->ranks = 2; in skl_dram_get_channel_info()
354 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1) in skl_dram_get_channel_info()
355 ch->ranks = 2; in skl_dram_get_channel_info()
357 ch->ranks = 1; in skl_dram_get_channel_info()
359 ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) || in skl_dram_get_channel_info()
360 skl_is_16gb_dimm(&ch->dimm_s); in skl_dram_get_channel_info()
362 drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n", in skl_dram_get_channel_info()
363 channel, ch->ranks, str_yes_no(ch->is_16gb_dimm)); in skl_dram_get_channel_info()
373 (ch0->dimm_s.size == 0 || in intel_is_dram_symmetric()
374 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l))); in intel_is_dram_symmetric()
380 struct dram_info *dram_info = &i915->dram_info; in skl_dram_get_channels_info()
385 val = intel_uncore_read(&i915->uncore, in skl_dram_get_channels_info()
389 dram_info->num_channels++; in skl_dram_get_channels_info()
391 val = intel_uncore_read(&i915->uncore, in skl_dram_get_channels_info()
395 dram_info->num_channels++; in skl_dram_get_channels_info()
397 if (dram_info->num_channels == 0) { in skl_dram_get_channels_info()
398 drm_info(&i915->drm, "Number of memory channels is zero\n"); in skl_dram_get_channels_info()
399 return -EINVAL; in skl_dram_get_channels_info()
403 drm_info(&i915->drm, "couldn't get memory rank information\n"); in skl_dram_get_channels_info()
404 return -EINVAL; in skl_dram_get_channels_info()
407 dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm; in skl_dram_get_channels_info()
409 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1); in skl_dram_get_channels_info()
411 drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n", in skl_dram_get_channels_info()
412 str_yes_no(dram_info->symmetric_memory)); in skl_dram_get_channels_info()
422 val = intel_uncore_read(&i915->uncore, in skl_get_dram_type()
443 struct dram_info *dram_info = &i915->dram_info; in skl_get_dram_info()
446 dram_info->type = skl_get_dram_type(i915); in skl_get_dram_info()
447 drm_dbg_kms(&i915->drm, "DRAM type: %s\n", in skl_get_dram_info()
448 intel_dram_type_str(dram_info->type)); in skl_get_dram_info()
525 dimm->width = bxt_get_dimm_width(val); in bxt_get_dimm_info()
526 dimm->ranks = bxt_get_dimm_ranks(val); in bxt_get_dimm_info()
530 * Gb to match the way we report this for non-LP platforms. in bxt_get_dimm_info()
532 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm); in bxt_get_dimm_info()
537 struct dram_info *dram_info = &i915->dram_info; in bxt_get_dram_info()
549 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i)); in bxt_get_dram_info()
553 dram_info->num_channels++; in bxt_get_dram_info()
558 drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN && in bxt_get_dram_info()
559 dram_info->type != INTEL_DRAM_UNKNOWN && in bxt_get_dram_info()
560 dram_info->type != type); in bxt_get_dram_info()
562 drm_dbg_kms(&i915->drm, in bxt_get_dram_info()
564 i - BXT_D_CR_DRP0_DUNIT_START, in bxt_get_dram_info()
572 dram_info->type = type; in bxt_get_dram_info()
575 if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) { in bxt_get_dram_info()
576 drm_info(&i915->drm, "couldn't get memory information\n"); in bxt_get_dram_info()
577 return -EINVAL; in bxt_get_dram_info()
585 struct dram_info *dram_info = &dev_priv->dram_info; in icl_pcode_read_mem_global_info()
589 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in icl_pcode_read_mem_global_info()
597 dram_info->type = INTEL_DRAM_DDR4; in icl_pcode_read_mem_global_info()
600 dram_info->type = INTEL_DRAM_DDR5; in icl_pcode_read_mem_global_info()
603 dram_info->type = INTEL_DRAM_LPDDR5; in icl_pcode_read_mem_global_info()
606 dram_info->type = INTEL_DRAM_LPDDR4; in icl_pcode_read_mem_global_info()
609 dram_info->type = INTEL_DRAM_DDR3; in icl_pcode_read_mem_global_info()
612 dram_info->type = INTEL_DRAM_LPDDR3; in icl_pcode_read_mem_global_info()
616 return -EINVAL; in icl_pcode_read_mem_global_info()
621 dram_info->type = INTEL_DRAM_DDR4; in icl_pcode_read_mem_global_info()
624 dram_info->type = INTEL_DRAM_DDR3; in icl_pcode_read_mem_global_info()
627 dram_info->type = INTEL_DRAM_LPDDR3; in icl_pcode_read_mem_global_info()
630 dram_info->type = INTEL_DRAM_LPDDR4; in icl_pcode_read_mem_global_info()
634 return -EINVAL; in icl_pcode_read_mem_global_info()
638 dram_info->num_channels = (val & 0xf0) >> 4; in icl_pcode_read_mem_global_info()
639 dram_info->num_qgv_points = (val & 0xf00) >> 8; in icl_pcode_read_mem_global_info()
640 dram_info->num_psf_gv_points = (val & 0x3000) >> 12; in icl_pcode_read_mem_global_info()
657 i915->dram_info.wm_lv_0_adjust_needed = false; in gen12_get_dram_info()
664 u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); in xelpdp_get_dram_info()
665 struct dram_info *dram_info = &i915->dram_info; in xelpdp_get_dram_info()
669 dram_info->type = INTEL_DRAM_DDR4; in xelpdp_get_dram_info()
672 dram_info->type = INTEL_DRAM_DDR5; in xelpdp_get_dram_info()
675 dram_info->type = INTEL_DRAM_LPDDR5; in xelpdp_get_dram_info()
678 dram_info->type = INTEL_DRAM_LPDDR4; in xelpdp_get_dram_info()
681 dram_info->type = INTEL_DRAM_DDR3; in xelpdp_get_dram_info()
684 dram_info->type = INTEL_DRAM_LPDDR3; in xelpdp_get_dram_info()
687 drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); in xelpdp_get_dram_info()
688 dram_info->type = INTEL_DRAM_GDDR; in xelpdp_get_dram_info()
691 drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); in xelpdp_get_dram_info()
692 dram_info->type = INTEL_DRAM_GDDR_ECC; in xelpdp_get_dram_info()
696 return -EINVAL; in xelpdp_get_dram_info()
699 dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); in xelpdp_get_dram_info()
700 dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); in xelpdp_get_dram_info()
708 struct dram_info *dram_info = &i915->dram_info; in intel_dram_detect()
721 dram_info->wm_lv_0_adjust_needed = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915); in intel_dram_detect()
736 drm_dbg_kms(&i915->drm, "Num qgv points %u\n", dram_info->num_qgv_points); in intel_dram_detect()
738 drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels); in intel_dram_detect()
740 drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n", in intel_dram_detect()
741 str_yes_no(dram_info->wm_lv_0_adjust_needed)); in intel_dram_detect()
761 edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP); in intel_dram_edram_detect()
773 i915->edram_size_mb = 128; in intel_dram_edram_detect()
775 i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap); in intel_dram_edram_detect()
777 drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb); in intel_dram_edram_detect()