pvr_rogue_cr_defs.h - OpenGrok cross reference for /linux-6.14.4/drivers/gpu/drm/imagination/pvr_rogue_cr

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16 #define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_SHIFT 0U
22 #define ROGUE_CR_PBE_INDIRECT_ADDRESS_SHIFT 0U
28 #define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_SHIFT 0U
34 #define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_SHIFT 0U
40 #define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_SHIFT 0U
46 #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_SHIFT 0U
52 #define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_SHIFT 0U
58 #define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_SHIFT 0U
64 #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_SHIFT 0U
70 #define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_SHIFT 0U
76 #define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_SHIFT 0U
82 #define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_SHIFT 0U
90 #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_SHIFT 62U
95 #define ROGUE_CR_CLK_CTRL_IPP_SHIFT 60U
100 #define ROGUE_CR_CLK_CTRL_FBC_SHIFT 58U
105 #define ROGUE_CR_CLK_CTRL_FBDC_SHIFT 56U
110 #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_SHIFT 54U
115 #define ROGUE_CR_CLK_CTRL_USCS_SHIFT 52U
120 #define ROGUE_CR_CLK_CTRL_PBE_SHIFT 50U
125 #define ROGUE_CR_CLK_CTRL_MCU_L1_SHIFT 48U
130 #define ROGUE_CR_CLK_CTRL_CDM_SHIFT 46U
135 #define ROGUE_CR_CLK_CTRL_SIDEKICK_SHIFT 44U
140 #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_SHIFT 42U
145 #define ROGUE_CR_CLK_CTRL_BIF_SHIFT 40U
150 #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_SHIFT 28U
155 #define ROGUE_CR_CLK_CTRL_MCU_L0_SHIFT 26U
160 #define ROGUE_CR_CLK_CTRL_TPU_SHIFT 24U
165 #define ROGUE_CR_CLK_CTRL_USC_SHIFT 20U
170 #define ROGUE_CR_CLK_CTRL_TLA_SHIFT 18U
175 #define ROGUE_CR_CLK_CTRL_SLC_SHIFT 16U
180 #define ROGUE_CR_CLK_CTRL_UVS_SHIFT 14U
185 #define ROGUE_CR_CLK_CTRL_PDS_SHIFT 12U
190 #define ROGUE_CR_CLK_CTRL_VDM_SHIFT 10U
195 #define ROGUE_CR_CLK_CTRL_PM_SHIFT 8U
200 #define ROGUE_CR_CLK_CTRL_GPP_SHIFT 6U
205 #define ROGUE_CR_CLK_CTRL_TE_SHIFT 4U
210 #define ROGUE_CR_CLK_CTRL_TSP_SHIFT 2U
215 #define ROGUE_CR_CLK_CTRL_ISP_SHIFT 0U
226 #define ROGUE_CR_CLK_STATUS_MCU_FBTC_SHIFT 32U
230 #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_SHIFT 31U
234 #define ROGUE_CR_CLK_STATUS_IPP_SHIFT 30U
238 #define ROGUE_CR_CLK_STATUS_FBC_SHIFT 29U
242 #define ROGUE_CR_CLK_STATUS_FBDC_SHIFT 28U
246 #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_SHIFT 27U
250 #define ROGUE_CR_CLK_STATUS_USCS_SHIFT 26U
254 #define ROGUE_CR_CLK_STATUS_PBE_SHIFT 25U
258 #define ROGUE_CR_CLK_STATUS_MCU_L1_SHIFT 24U
262 #define ROGUE_CR_CLK_STATUS_CDM_SHIFT 23U
266 #define ROGUE_CR_CLK_STATUS_SIDEKICK_SHIFT 22U
270 #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_SHIFT 21U
274 #define ROGUE_CR_CLK_STATUS_BIF_SHIFT 20U
278 #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_SHIFT 14U
282 #define ROGUE_CR_CLK_STATUS_MCU_L0_SHIFT 13U
286 #define ROGUE_CR_CLK_STATUS_TPU_SHIFT 12U
290 #define ROGUE_CR_CLK_STATUS_USC_SHIFT 10U
294 #define ROGUE_CR_CLK_STATUS_TLA_SHIFT 9U
298 #define ROGUE_CR_CLK_STATUS_SLC_SHIFT 8U
302 #define ROGUE_CR_CLK_STATUS_UVS_SHIFT 7U
306 #define ROGUE_CR_CLK_STATUS_PDS_SHIFT 6U
310 #define ROGUE_CR_CLK_STATUS_VDM_SHIFT 5U
314 #define ROGUE_CR_CLK_STATUS_PM_SHIFT 4U
318 #define ROGUE_CR_CLK_STATUS_GPP_SHIFT 3U
322 #define ROGUE_CR_CLK_STATUS_TE_SHIFT 2U
326 #define ROGUE_CR_CLK_STATUS_TSP_SHIFT 1U
330 #define ROGUE_CR_CLK_STATUS_ISP_SHIFT 0U
338 #define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_SHIFT 48U
340 #define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_SHIFT 32U
342 #define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_SHIFT 16U
344 #define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_SHIFT 0U
350 #define ROGUE_CR_CORE_ID_ID_SHIFT 16U
352 #define ROGUE_CR_CORE_ID_CONFIG_SHIFT 0U
358 #define ROGUE_CR_CORE_REVISION_DESIGNER_SHIFT 24U
360 #define ROGUE_CR_CORE_REVISION_MAJOR_SHIFT 16U
362 #define ROGUE_CR_CORE_REVISION_MINOR_SHIFT 8U
364 #define ROGUE_CR_CORE_REVISION_MAINTENANCE_SHIFT 0U
370 #define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0U
376 #define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0U
382 #define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_SHIFT 0U
388 #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_SHIFT 36U
393 #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_SHIFT 34U
398 #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_SHIFT 32U
403 #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_SHIFT 30U
408 #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_SHIFT 28U
413 #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_SHIFT 26U
418 #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_SHIFT 24U
423 #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_SHIFT 22U
428 #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_SHIFT 20U
433 #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_SHIFT 18U
438 #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_SHIFT 16U
447 #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_SHIFT 10U
451 #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_SHIFT 9U
455 #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_SHIFT 8U
459 #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_SHIFT 7U
463 #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_SHIFT 6U
467 #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_SHIFT 5U
471 #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_SHIFT 4U
475 #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_SHIFT 3U
479 #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_SHIFT 2U
483 #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_SHIFT 1U
487 #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_SHIFT 0U
496 #define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_SHIFT 63U
499 #define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_SHIFT 62U
502 #define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_SHIFT 61U
505 #define ROGUE_CR_SOFT_RESET_JONES_CORE_SHIFT 60U
508 #define ROGUE_CR_SOFT_RESET_TILING_CORE_SHIFT 59U
511 #define ROGUE_CR_SOFT_RESET_TE3_SHIFT 58U
514 #define ROGUE_CR_SOFT_RESET_VCE_SHIFT 57U
517 #define ROGUE_CR_SOFT_RESET_VBS_SHIFT 56U
520 #define ROGUE_CR_SOFT_RESET_DPX1_CORE_SHIFT 55U
523 #define ROGUE_CR_SOFT_RESET_DPX0_CORE_SHIFT 54U
526 #define ROGUE_CR_SOFT_RESET_FBA_SHIFT 53U
529 #define ROGUE_CR_SOFT_RESET_FB_CDC_SHIFT 51U
532 #define ROGUE_CR_SOFT_RESET_SH_SHIFT 50U
535 #define ROGUE_CR_SOFT_RESET_VRDM_SHIFT 49U
538 #define ROGUE_CR_SOFT_RESET_MCU_FBTC_SHIFT 48U
541 #define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_SHIFT 47U
544 #define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_SHIFT 46U
547 #define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_SHIFT 45U
550 #define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_SHIFT 44U
553 #define ROGUE_CR_SOFT_RESET_IPP_SHIFT 43U
556 #define ROGUE_CR_SOFT_RESET_BIF_TEXAS_SHIFT 42U
559 #define ROGUE_CR_SOFT_RESET_TORNADO_CORE_SHIFT 41U
562 #define ROGUE_CR_SOFT_RESET_DUST_H_CORE_SHIFT 40U
565 #define ROGUE_CR_SOFT_RESET_DUST_G_CORE_SHIFT 39U
568 #define ROGUE_CR_SOFT_RESET_DUST_F_CORE_SHIFT 38U
571 #define ROGUE_CR_SOFT_RESET_DUST_E_CORE_SHIFT 37U
574 #define ROGUE_CR_SOFT_RESET_DUST_D_CORE_SHIFT 36U
577 #define ROGUE_CR_SOFT_RESET_DUST_C_CORE_SHIFT 35U
580 #define ROGUE_CR_SOFT_RESET_MMU_SHIFT 34U
583 #define ROGUE_CR_SOFT_RESET_BIF1_SHIFT 33U
586 #define ROGUE_CR_SOFT_RESET_GARTEN_SHIFT 32U
589 #define ROGUE_CR_SOFT_RESET_CPU_SHIFT 32U
592 #define ROGUE_CR_SOFT_RESET_RASCAL_CORE_SHIFT 31U
595 #define ROGUE_CR_SOFT_RESET_DUST_B_CORE_SHIFT 30U
598 #define ROGUE_CR_SOFT_RESET_DUST_A_CORE_SHIFT 29U
601 #define ROGUE_CR_SOFT_RESET_FB_TLCACHE_SHIFT 28U
604 #define ROGUE_CR_SOFT_RESET_SLC_SHIFT 27U
607 #define ROGUE_CR_SOFT_RESET_TLA_SHIFT 26U
610 #define ROGUE_CR_SOFT_RESET_UVS_SHIFT 25U
613 #define ROGUE_CR_SOFT_RESET_TE_SHIFT 24U
616 #define ROGUE_CR_SOFT_RESET_GPP_SHIFT 23U
619 #define ROGUE_CR_SOFT_RESET_FBDC_SHIFT 22U
622 #define ROGUE_CR_SOFT_RESET_FBC_SHIFT 21U
625 #define ROGUE_CR_SOFT_RESET_PM_SHIFT 20U
628 #define ROGUE_CR_SOFT_RESET_PBE_SHIFT 19U
631 #define ROGUE_CR_SOFT_RESET_USC_SHARED_SHIFT 18U
634 #define ROGUE_CR_SOFT_RESET_MCU_L1_SHIFT 17U
637 #define ROGUE_CR_SOFT_RESET_BIF_SHIFT 16U
640 #define ROGUE_CR_SOFT_RESET_CDM_SHIFT 15U
643 #define ROGUE_CR_SOFT_RESET_VDM_SHIFT 14U
646 #define ROGUE_CR_SOFT_RESET_TESS_SHIFT 13U
649 #define ROGUE_CR_SOFT_RESET_PDS_SHIFT 12U
652 #define ROGUE_CR_SOFT_RESET_ISP_SHIFT 11U
655 #define ROGUE_CR_SOFT_RESET_TSP_SHIFT 10U
658 #define ROGUE_CR_SOFT_RESET_SYSARB_SHIFT 5U
661 #define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_SHIFT 4U
664 #define ROGUE_CR_SOFT_RESET_MCU_L0_SHIFT 3U
667 #define ROGUE_CR_SOFT_RESET_TPU_SHIFT 2U
670 #define ROGUE_CR_SOFT_RESET_USC_SHIFT 0U
677 #define ROGUE_CR_SOFT_RESET2_SPFILTER_SHIFT 12U
679 #define ROGUE_CR_SOFT_RESET2_TDM_SHIFT 11U
682 #define ROGUE_CR_SOFT_RESET2_ASTC_SHIFT 10U
685 #define ROGUE_CR_SOFT_RESET2_BLACKPEARL_SHIFT 9U
688 #define ROGUE_CR_SOFT_RESET2_USCPS_SHIFT 8U
691 #define ROGUE_CR_SOFT_RESET2_IPF_SHIFT 7U
694 #define ROGUE_CR_SOFT_RESET2_GEOMETRY_SHIFT 6U
697 #define ROGUE_CR_SOFT_RESET2_USC_SHARED_SHIFT 5U
700 #define ROGUE_CR_SOFT_RESET2_PDS_SHARED_SHIFT 4U
703 #define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_SHIFT 3U
706 #define ROGUE_CR_SOFT_RESET2_PIXEL_SHIFT 2U
709 #define ROGUE_CR_SOFT_RESET2_CDM_SHIFT 1U
712 #define ROGUE_CR_SOFT_RESET2_VERTEX_SHIFT 0U
721 #define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_SHIFT 31U
724 #define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_SHIFT 30U
727 #define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_SHIFT 29U
730 #define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_SHIFT 28U
733 #define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_SHIFT 27U
736 #define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_SHIFT 26U
739 #define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_SHIFT 25U
742 #define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_SHIFT 24U
745 #define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_SHIFT 23U
748 #define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_SHIFT 22U
751 #define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_SHIFT 21U
754 #define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_SHIFT 20U
757 #define ROGUE_CR_EVENT_STATUS_SAFETY_SHIFT 20U
760 #define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_SHIFT 19U
763 #define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_SHIFT 19U
766 #define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_SHIFT 18U
769 #define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U
772 #define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_SHIFT 17U
775 #define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_SHIFT 17U
778 #define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_SHIFT 16U
781 #define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_SHIFT 15U
784 #define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_SHIFT 14U
787 #define ROGUE_CR_EVENT_STATUS_GPIO_ACK_SHIFT 13U
790 #define ROGUE_CR_EVENT_STATUS_GPIO_REQ_SHIFT 12U
793 #define ROGUE_CR_EVENT_STATUS_POWER_ABORT_SHIFT 11U
796 #define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_SHIFT 10U
799 #define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_SHIFT 9U
802 #define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_SHIFT 8U
805 #define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_SHIFT 7U
808 #define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 6U
811 #define ROGUE_CR_EVENT_STATUS_TA_FINISHED_SHIFT 5U
814 #define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_SHIFT 4U
817 #define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 3U
820 #define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_SHIFT 2U
823 #define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_SHIFT 1U
826 #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_SHIFT 0U
833 #define ROGUE_CR_TIMER_BIT31_SHIFT 63U
836 #define ROGUE_CR_TIMER_VALUE_SHIFT 0U
842 #define ROGUE_CR_TLA_STATUS_BLIT_COUNT_SHIFT 39U
844 #define ROGUE_CR_TLA_STATUS_REQUEST_SHIFT 7U
846 #define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_SHIFT 1U
848 #define ROGUE_CR_TLA_STATUS_BUSY_SHIFT 0U
855 #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_SHIFT 0U
862 #define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_SHIFT 6U
865 #define ROGUE_CR_SIDEKICK_IDLE_MMU_SHIFT 5U
868 #define ROGUE_CR_SIDEKICK_IDLE_BIF128_SHIFT 4U
871 #define ROGUE_CR_SIDEKICK_IDLE_TLA_SHIFT 3U
874 #define ROGUE_CR_SIDEKICK_IDLE_GARTEN_SHIFT 2U
877 #define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_SHIFT 1U
880 #define ROGUE_CR_SIDEKICK_IDLE_SOCIF_SHIFT 0U
887 #define ROGUE_CR_MARS_IDLE_MH_SYSARB0_SHIFT 2U
890 #define ROGUE_CR_MARS_IDLE_CPU_SHIFT 1U
893 #define ROGUE_CR_MARS_IDLE_SOCIF_SHIFT 0U
900 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_SHIFT 4U
902 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U
905 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U
912 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_SHIFT 32U
914 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_SHIFT 0U
920 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_SHIFT 0U
926 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_SHIFT 32U
928 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_SHIFT 0U
934 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_SHIFT 32U
936 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_SHIFT 0U
942 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_SHIFT 0U
948 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_SHIFT 32U
950 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_SHIFT 0U
956 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U
959 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U
966 #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_SHIFT 36U
968 #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSHIFT 4U
969 #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSIZE 16U
970 #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_SHIFT 4U
972 #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSHIFT 4U
973 #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSIZE 16U
979 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
982 #define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_SHIFT 29U
985 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
988 #define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_SHIFT 28U
991 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
994 #define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_SHIFT 27U
997 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
999 #define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_SHIFT 21U
1001 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
1004 #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_SHIFT 20U
1007 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
1009 #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_SHIFT 11U
1011 #define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_SHIFT 7U
1013 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
1015 #define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_SHIFT 1U
1017 #define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_SHIFT 0U
1024 #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_SHIFT 36U
1026 #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSHIFT 4U
1027 #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSIZE 16U
1028 #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_SHIFT 4U
1030 #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSHIFT 4U
1031 #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSIZE 16U
1037 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
1040 #define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_SHIFT 29U
1043 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
1046 #define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_SHIFT 28U
1049 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
1052 #define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_SHIFT 27U
1055 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
1057 #define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_SHIFT 21U
1059 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
1062 #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_SHIFT 20U
1065 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
1067 #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_SHIFT 11U
1069 #define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_SHIFT 7U
1071 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
1073 #define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_SHIFT 1U
1075 #define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_SHIFT 0U
1082 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_SHIFT 36U
1084 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSHIFT 4U
1085 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSIZE 16U
1086 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_SHIFT 4U
1088 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSHIFT 4U
1089 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSIZE 16U
1095 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
1098 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_SHIFT 29U
1101 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
1104 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_SHIFT 28U
1107 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
1110 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_SHIFT 27U
1113 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
1115 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_SHIFT 21U
1117 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
1120 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_SHIFT 20U
1123 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
1125 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_SHIFT 11U
1127 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_SHIFT 7U
1129 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
1131 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_SHIFT 1U
1133 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_SHIFT 0U
1140 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_SHIFT 40U
1143 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_SHIFT 33U
1146 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_SHIFT 32U
1149 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_SHIFT 25U
1151 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_SHIFT 24U
1154 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_SHIFT 16U
1158 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_SHIFT 0U
1164 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1166 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_SHIFT 0U
1173 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_SHIFT 12U
1175 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_SHIFT 6U
1177 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_SHIFT 5U
1180 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1186 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1188 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_SHIFT 0U
1195 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_SHIFT 12U
1197 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_SHIFT 6U
1199 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_SHIFT 5U
1202 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1208 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1210 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_SHIFT 0U
1217 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_SHIFT 12U
1219 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_SHIFT 6U
1221 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_SHIFT 5U
1224 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1230 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1232 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_SHIFT 0U
1239 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_SHIFT 12U
1241 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_SHIFT 6U
1243 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_SHIFT 5U
1246 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1252 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1254 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_SHIFT 0U
1261 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_SHIFT 12U
1263 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_SHIFT 6U
1265 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_SHIFT 5U
1268 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1274 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_SHIFT 32U
1277 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_SHIFT 0U
1283 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_SHIFT 0U
1290 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_SHIFT 36U
1292 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_SHIFT 32U
1294 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_SHIFT 12U
1296 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_SHIFT 11U
1299 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_SHIFT 7U
1310 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_SHIFT 1U
1312 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_SHIFT 0U
1319 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_SHIFT 1U
1321 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_SHIFT 0U
1328 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_SHIFT 36U
1330 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_SHIFT 32U
1332 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_SHIFT 12U
1334 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_SHIFT 11U
1337 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_SHIFT 7U
1339 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_SHIFT 0U
1346 #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_SHIFT 0U
1353 #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_SHIFT 0U
1360 #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_SHIFT 0U
1367 #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_SHIFT 0U
1374 #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_SHIFT 0U
1381 #define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_SHIFT 0U
1388 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_SHIFT 5U
1391 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_SHIFT 4U
1394 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_SHIFT 3U
1397 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_SHIFT 2U
1400 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_SHIFT 1U
1403 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_SHIFT 0U
1410 #define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_SHIFT 0U
1416 #define ROGUE_CR_XPU_BROADCAST_MASK_SHIFT 0U
1422 #define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_SHIFT 0U
1428 #define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_SHIFT 0U
1434 #define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_SHIFT 2U
1436 #define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_SHIFT 1U
1439 #define ROGUE_CR_META_SP_MSLVCTRL0_RD_SHIFT 0U
1446 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_SHIFT 30U
1448 #define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_SHIFT 29U
1451 #define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_SHIFT 28U
1454 #define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_SHIFT 26U
1457 #define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_SHIFT 25U
1460 #define ROGUE_CR_META_SP_MSLVCTRL1_READY_SHIFT 24U
1463 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_SHIFT 21U
1465 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_SHIFT 20U
1468 #define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_SHIFT 18U
1471 #define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_SHIFT 4U
1473 #define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_SHIFT 2U
1475 #define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_SHIFT 0U
1481 #define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_SHIFT 2U
1483 #define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_SHIFT 0U
1489 #define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_SHIFT 0U
1495 #define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_SHIFT 0U
1501 #define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_SHIFT 0U
1507 #define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_SHIFT 0U
1513 #define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_SHIFT 0U
1519 #define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_SHIFT 0U
1525 #define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_SHIFT 0U
1531 #define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_SHIFT 0U
1537 #define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_SHIFT 0U
1544 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_SHIFT 3U
1547 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_SHIFT 2U
1554 #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_SHIFT 3U
1557 #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_SHIFT 2U
1564 #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_SHIFT 0U
1571 #define ROGUE_CR_MTS_SCHEDULE_HOST_SHIFT 8U
1575 #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_SHIFT 6U
1581 #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_SHIFT 5U
1585 #define ROGUE_CR_MTS_SCHEDULE_TASK_SHIFT 4U
1589 #define ROGUE_CR_MTS_SCHEDULE_DM_SHIFT 0U
1604 #define ROGUE_CR_MTS_SCHEDULE1_HOST_SHIFT 8U
1608 #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_SHIFT 6U
1614 #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_SHIFT 5U
1618 #define ROGUE_CR_MTS_SCHEDULE1_TASK_SHIFT 4U
1622 #define ROGUE_CR_MTS_SCHEDULE1_DM_SHIFT 0U
1637 #define ROGUE_CR_MTS_SCHEDULE2_HOST_SHIFT 8U
1641 #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_SHIFT 6U
1647 #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_SHIFT 5U
1651 #define ROGUE_CR_MTS_SCHEDULE2_TASK_SHIFT 4U
1655 #define ROGUE_CR_MTS_SCHEDULE2_DM_SHIFT 0U
1670 #define ROGUE_CR_MTS_SCHEDULE3_HOST_SHIFT 8U
1674 #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_SHIFT 6U
1680 #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_SHIFT 5U
1684 #define ROGUE_CR_MTS_SCHEDULE3_TASK_SHIFT 4U
1688 #define ROGUE_CR_MTS_SCHEDULE3_DM_SHIFT 0U
1703 #define ROGUE_CR_MTS_SCHEDULE4_HOST_SHIFT 8U
1707 #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_SHIFT 6U
1713 #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_SHIFT 5U
1717 #define ROGUE_CR_MTS_SCHEDULE4_TASK_SHIFT 4U
1721 #define ROGUE_CR_MTS_SCHEDULE4_DM_SHIFT 0U
1736 #define ROGUE_CR_MTS_SCHEDULE5_HOST_SHIFT 8U
1740 #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_SHIFT 6U
1746 #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_SHIFT 5U
1750 #define ROGUE_CR_MTS_SCHEDULE5_TASK_SHIFT 4U
1754 #define ROGUE_CR_MTS_SCHEDULE5_DM_SHIFT 0U
1769 #define ROGUE_CR_MTS_SCHEDULE6_HOST_SHIFT 8U
1773 #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_SHIFT 6U
1779 #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_SHIFT 5U
1783 #define ROGUE_CR_MTS_SCHEDULE6_TASK_SHIFT 4U
1787 #define ROGUE_CR_MTS_SCHEDULE6_DM_SHIFT 0U
1802 #define ROGUE_CR_MTS_SCHEDULE7_HOST_SHIFT 8U
1806 #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_SHIFT 6U
1812 #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_SHIFT 5U
1816 #define ROGUE_CR_MTS_SCHEDULE7_TASK_SHIFT 4U
1820 #define ROGUE_CR_MTS_SCHEDULE7_DM_SHIFT 0U
1835 #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U
1841 #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U
1847 #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U
1853 #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U
1860 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT 44U
1862 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_SHIFT 44U
1864 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT 40U
1866 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_SHIFT 12U
1868 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_SHIFT 9U
1870 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_SHIFT 8U
1873 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_SHIFT 0U
1881 #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1887 #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1893 #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1899 #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1905 #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1911 #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1917 #define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_SHIFT 22U
1919 #define ROGUE_CR_MTS_INTCTX_DM_PTR_SHIFT 18U
1921 #define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_SHIFT 16U
1923 #define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_SHIFT 8U
1925 #define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_SHIFT 0U
1931 #define ROGUE_CR_MTS_BGCTX_DM_PTR_SHIFT 10U
1933 #define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_SHIFT 8U
1935 #define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_SHIFT 0U
1941 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_SHIFT 56U
1943 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_SHIFT 48U
1945 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_SHIFT 40U
1947 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_SHIFT 32U
1949 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_SHIFT 24U
1951 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_SHIFT 16U
1953 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_SHIFT 8U
1955 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_SHIFT 0U
1961 #define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_SHIFT 0U
1967 #define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_SHIFT 0U
1973 #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_SHIFT 0U
1980 #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_SHIFT 0U
1987 #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_SHIFT 0U
1994 #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_SHIFT 0U
2001 #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_SHIFT 0U
2008 #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_SHIFT 0U
2015 #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_SHIFT 0U
2022 #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_SHIFT 0U
2029 #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_SHIFT 0U
2036 #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_SHIFT 0U
2043 #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_SHIFT 0U
2050 #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_SHIFT 0U
2057 #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_SHIFT 0U
2064 #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_SHIFT 0U
2071 #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_SHIFT 0U
2078 #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_SHIFT 0U
2085 #define ROGUE_CR_META_BOOT_MODE_SHIFT 0U
2092 #define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_SHIFT 0U
2099 #define ROGUE_CR_PPP_CHECKSUM_SHIFT 0U
2123 #define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_SHIFT 8U
2126 #define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_SHIFT 7U
2129 #define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_SHIFT 6U
2132 #define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_SHIFT 5U
2135 #define ROGUE_CR_ISP_RENDER_RESUME_SHIFT 4U
2138 #define ROGUE_CR_ISP_RENDER_DIR_SHIFT 2U
2144 #define ROGUE_CR_ISP_RENDER_MODE_SHIFT 0U
2153 #define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_SHIFT 31U
2156 #define ROGUE_CR_ISP_CTL_LINE_STYLE_SHIFT 30U
2159 #define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_SHIFT 29U
2162 #define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_SHIFT 28U
2165 #define ROGUE_CR_ISP_CTL_PAIR_TILES_SHIFT 27U
2168 #define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_SHIFT 26U
2171 #define ROGUE_CR_ISP_CTL_TILE_AGE_EN_SHIFT 25U
2174 #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_SHIFT 23U
2179 #define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_SHIFT 21U
2181 #define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_SHIFT 20U
2184 #define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_SHIFT 19U
2187 #define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_SHIFT 18U
2190 #define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_SHIFT 17U
2193 #define ROGUE_CR_ISP_CTL_SAMPLE_POS_SHIFT 16U
2196 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_SHIFT 12U
2214 #define ROGUE_CR_ISP_CTL_VALID_ID_SHIFT 4U
2216 #define ROGUE_CR_ISP_CTL_UPASS_START_SHIFT 0U
2222 #define ROGUE_CR_ISP_STATUS_SPLIT_MAX_SHIFT 2U
2225 #define ROGUE_CR_ISP_STATUS_ACTIVE_SHIFT 1U
2228 #define ROGUE_CR_ISP_STATUS_EOR_SHIFT 0U
2233 #define ROGUE_CR_ISP_XTP_RESUME_REPEATCOUNT 64U
2237 #define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_SHIFT 12U
2239 #define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_SHIFT 0U
2243 #define ROGUE_CR_ISP_XTP_STORE_REPEATCOUNT 32U
2247 #define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_SHIFT 30U
2250 #define ROGUE_CR_ISP_XTP_STORE0_EOR_SHIFT 29U
2253 #define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_SHIFT 28U
2256 #define ROGUE_CR_ISP_XTP_STORE0_MT_SHIFT 24U
2258 #define ROGUE_CR_ISP_XTP_STORE0_TILE_X_SHIFT 12U
2260 #define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_SHIFT 0U
2264 #define ROGUE_CR_BIF_CAT_BASE_REPEATCOUNT 8U
2268 #define ROGUE_CR_BIF_CAT_BASE0_ADDR_SHIFT 12U
2270 #define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSHIFT 12U
2271 #define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSIZE 4096U
2276 #define ROGUE_CR_BIF_CAT_BASE1_ADDR_SHIFT 12U
2278 #define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSHIFT 12U
2279 #define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSIZE 4096U
2284 #define ROGUE_CR_BIF_CAT_BASE2_ADDR_SHIFT 12U
2286 #define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSHIFT 12U
2287 #define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSIZE 4096U
2292 #define ROGUE_CR_BIF_CAT_BASE3_ADDR_SHIFT 12U
2294 #define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSHIFT 12U
2295 #define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSIZE 4096U
2300 #define ROGUE_CR_BIF_CAT_BASE4_ADDR_SHIFT 12U
2302 #define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSHIFT 12U
2303 #define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSIZE 4096U
2308 #define ROGUE_CR_BIF_CAT_BASE5_ADDR_SHIFT 12U
2310 #define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSHIFT 12U
2311 #define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSIZE 4096U
2316 #define ROGUE_CR_BIF_CAT_BASE6_ADDR_SHIFT 12U
2318 #define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSHIFT 12U
2319 #define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSIZE 4096U
2324 #define ROGUE_CR_BIF_CAT_BASE7_ADDR_SHIFT 12U
2326 #define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSHIFT 12U
2327 #define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSIZE 4096U
2332 #define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_SHIFT 48U
2334 #define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_SHIFT 40U
2336 #define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_SHIFT 32U
2338 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_SHIFT 24U
2340 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_SHIFT 19U
2342 #define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_SHIFT 16U
2344 #define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_SHIFT 8U
2346 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_SHIFT 0U
2352 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_SHIFT 40U
2354 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_SHIFT 12U
2356 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_SHIFT 1U
2359 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_SHIFT 0U
2366 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_SHIFT 40U
2368 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_SHIFT 12U
2370 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_SHIFT 1U
2373 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_SHIFT 0U
2380 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT 40U
2382 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_SHIFT 12U
2384 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_SHIFT 1U
2387 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_SHIFT 0U
2394 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_SHIFT 40U
2396 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_SHIFT 12U
2398 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_SHIFT 1U
2401 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_SHIFT 0U
2408 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_SHIFT 40U
2410 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_SHIFT 12U
2412 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_SHIFT 1U
2415 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_SHIFT 0U
2422 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT 40U
2424 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_SHIFT 12U
2426 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_SHIFT 1U
2429 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_SHIFT 0U
2436 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_SHIFT 12U
2438 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_SHIFT 4U
2440 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_SHIFT 0U
2446 #define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_SHIFT 1U
2449 #define ROGUE_CR_BIF_MMU_ENTRY_PENDING_SHIFT 0U
2456 #define ROGUE_CR_BIF_CTRL_INVAL_TLB1_SHIFT 3U
2459 #define ROGUE_CR_BIF_CTRL_INVAL_PC_SHIFT 2U
2462 #define ROGUE_CR_BIF_CTRL_INVAL_PD_SHIFT 1U
2465 #define ROGUE_CR_BIF_CTRL_INVAL_PT_SHIFT 0U
2473 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_SHIFT 9U
2476 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_SHIFT 8U
2479 #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_SHIFT 7U
2482 #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_SHIFT 6U
2485 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_SHIFT 5U
2488 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_SHIFT 4U
2491 #define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_SHIFT 3U
2494 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_SHIFT 2U
2497 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_SHIFT 1U
2500 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_SHIFT 0U
2507 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U
2509 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U
2511 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U
2513 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U
2516 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
2519 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U
2527 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_SHIFT 52U
2530 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U
2533 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_SHIFT 46U
2535 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U
2537 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U
2539 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_SHIFT 40U
2541 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U
2543 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
2544 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
2549 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_SHIFT 12U
2551 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_SHIFT 8U
2553 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_SHIFT 5U
2555 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_SHIFT 4U
2558 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
2561 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_SHIFT 0U
2568 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_SHIFT 50U
2571 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_SHIFT 44U
2573 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_SHIFT 40U
2575 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_SHIFT 4U
2577 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
2578 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
2584 #define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_SHIFT 28U
2587 #define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U
2589 #define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U
2591 #define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U
2593 #define ROGUE_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U
2596 #define ROGUE_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U
2599 #define ROGUE_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U
2604 #define ROGUE_CR_BIF_TILING_CFG_REPEATCOUNT 8U
2608 #define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_SHIFT 61U
2610 #define ROGUE_CR_BIF_TILING_CFG0_ENABLE_SHIFT 60U
2613 #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_SHIFT 32U
2615 #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSHIFT 12U
2616 #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSIZE 4096U
2617 #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_SHIFT 0U
2619 #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSHIFT 12U
2620 #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSIZE 4096U
2625 #define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_SHIFT 61U
2627 #define ROGUE_CR_BIF_TILING_CFG1_ENABLE_SHIFT 60U
2630 #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_SHIFT 32U
2632 #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSHIFT 12U
2633 #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSIZE 4096U
2634 #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_SHIFT 0U
2636 #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSHIFT 12U
2637 #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSIZE 4096U
2642 #define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_SHIFT 61U
2644 #define ROGUE_CR_BIF_TILING_CFG2_ENABLE_SHIFT 60U
2647 #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_SHIFT 32U
2649 #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSHIFT 12U
2650 #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSIZE 4096U
2651 #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_SHIFT 0U
2653 #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSHIFT 12U
2654 #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSIZE 4096U
2659 #define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_SHIFT 61U
2661 #define ROGUE_CR_BIF_TILING_CFG3_ENABLE_SHIFT 60U
2664 #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_SHIFT 32U
2666 #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSHIFT 12U
2667 #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSIZE 4096U
2668 #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_SHIFT 0U
2670 #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSHIFT 12U
2671 #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSIZE 4096U
2676 #define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_SHIFT 61U
2678 #define ROGUE_CR_BIF_TILING_CFG4_ENABLE_SHIFT 60U
2681 #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_SHIFT 32U
2683 #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSHIFT 12U
2684 #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSIZE 4096U
2685 #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_SHIFT 0U
2687 #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSHIFT 12U
2688 #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSIZE 4096U
2693 #define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_SHIFT 61U
2695 #define ROGUE_CR_BIF_TILING_CFG5_ENABLE_SHIFT 60U
2698 #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_SHIFT 32U
2700 #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSHIFT 12U
2701 #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSIZE 4096U
2702 #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_SHIFT 0U
2704 #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSHIFT 12U
2705 #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSIZE 4096U
2710 #define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_SHIFT 61U
2712 #define ROGUE_CR_BIF_TILING_CFG6_ENABLE_SHIFT 60U
2715 #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_SHIFT 32U
2717 #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSHIFT 12U
2718 #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSIZE 4096U
2719 #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_SHIFT 0U
2721 #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSHIFT 12U
2722 #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSIZE 4096U
2727 #define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_SHIFT 61U
2729 #define ROGUE_CR_BIF_TILING_CFG7_ENABLE_SHIFT 60U
2732 #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_SHIFT 32U
2734 #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSHIFT 12U
2735 #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSIZE 4096U
2736 #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_SHIFT 0U
2738 #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSHIFT 12U
2739 #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSIZE 4096U
2744 #define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_SHIFT 16U
2746 #define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_SHIFT 0U
2752 #define ROGUE_CR_BIF_READS_INT_STATUS_MMU_SHIFT 16U
2754 #define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_SHIFT 0U
2760 #define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_SHIFT 0U
2766 #define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_SHIFT 0U
2772 #define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_SHIFT 0U
2778 #define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_SHIFT 0U
2784 #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_SHIFT 4U
2786 #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSHIFT 4U
2787 #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSIZE 16U
2792 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U
2794 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U
2796 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U
2798 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U
2801 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
2804 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U
2811 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U
2814 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U
2816 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U
2818 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U
2820 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
2821 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
2826 #define ROGUE_CR_MCU_FENCE_DM_SHIFT 40U
2834 #define ROGUE_CR_MCU_FENCE_ADDR_SHIFT 5U
2836 #define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSHIFT 5U
2837 #define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSIZE 32U
2840 #define ROGUE_CR_SCRATCH_REPEATCOUNT 16U
2844 #define ROGUE_CR_SCRATCH0_DATA_SHIFT 0U
2850 #define ROGUE_CR_SCRATCH1_DATA_SHIFT 0U
2856 #define ROGUE_CR_SCRATCH2_DATA_SHIFT 0U
2862 #define ROGUE_CR_SCRATCH3_DATA_SHIFT 0U
2868 #define ROGUE_CR_SCRATCH4_DATA_SHIFT 0U
2874 #define ROGUE_CR_SCRATCH5_DATA_SHIFT 0U
2880 #define ROGUE_CR_SCRATCH6_DATA_SHIFT 0U
2886 #define ROGUE_CR_SCRATCH7_DATA_SHIFT 0U
2892 #define ROGUE_CR_SCRATCH8_DATA_SHIFT 0U
2898 #define ROGUE_CR_SCRATCH9_DATA_SHIFT 0U
2904 #define ROGUE_CR_SCRATCH10_DATA_SHIFT 0U
2910 #define ROGUE_CR_SCRATCH11_DATA_SHIFT 0U
2916 #define ROGUE_CR_SCRATCH12_DATA_SHIFT 0U
2922 #define ROGUE_CR_SCRATCH13_DATA_SHIFT 0U
2928 #define ROGUE_CR_SCRATCH14_DATA_SHIFT 0U
2934 #define ROGUE_CR_SCRATCH15_DATA_SHIFT 0U
2938 #define ROGUE_CR_OS0_SCRATCH_REPEATCOUNT 2U
2942 #define ROGUE_CR_OS0_SCRATCH0_DATA_SHIFT 0U
2948 #define ROGUE_CR_OS0_SCRATCH1_DATA_SHIFT 0U
2954 #define ROGUE_CR_OS0_SCRATCH2_DATA_SHIFT 0U
2960 #define ROGUE_CR_OS0_SCRATCH3_DATA_SHIFT 0U
2964 #define ROGUE_CR_OS1_SCRATCH_REPEATCOUNT 2U
2968 #define ROGUE_CR_OS1_SCRATCH0_DATA_SHIFT 0U
2974 #define ROGUE_CR_OS1_SCRATCH1_DATA_SHIFT 0U
2980 #define ROGUE_CR_OS1_SCRATCH2_DATA_SHIFT 0U
2986 #define ROGUE_CR_OS1_SCRATCH3_DATA_SHIFT 0U
2990 #define ROGUE_CR_OS2_SCRATCH_REPEATCOUNT 2U
2994 #define ROGUE_CR_OS2_SCRATCH0_DATA_SHIFT 0U
3000 #define ROGUE_CR_OS2_SCRATCH1_DATA_SHIFT 0U
3006 #define ROGUE_CR_OS2_SCRATCH2_DATA_SHIFT 0U
3012 #define ROGUE_CR_OS2_SCRATCH3_DATA_SHIFT 0U
3016 #define ROGUE_CR_OS3_SCRATCH_REPEATCOUNT 2U
3020 #define ROGUE_CR_OS3_SCRATCH0_DATA_SHIFT 0U
3026 #define ROGUE_CR_OS3_SCRATCH1_DATA_SHIFT 0U
3032 #define ROGUE_CR_OS3_SCRATCH2_DATA_SHIFT 0U
3038 #define ROGUE_CR_OS3_SCRATCH3_DATA_SHIFT 0U
3042 #define ROGUE_CR_OS4_SCRATCH_REPEATCOUNT 2U
3046 #define ROGUE_CR_OS4_SCRATCH0_DATA_SHIFT 0U
3052 #define ROGUE_CR_OS4_SCRATCH1_DATA_SHIFT 0U
3058 #define ROGUE_CR_OS4_SCRATCH2_DATA_SHIFT 0U
3064 #define ROGUE_CR_OS4_SCRATCH3_DATA_SHIFT 0U
3068 #define ROGUE_CR_OS5_SCRATCH_REPEATCOUNT 2U
3072 #define ROGUE_CR_OS5_SCRATCH0_DATA_SHIFT 0U
3078 #define ROGUE_CR_OS5_SCRATCH1_DATA_SHIFT 0U
3084 #define ROGUE_CR_OS5_SCRATCH2_DATA_SHIFT 0U
3090 #define ROGUE_CR_OS5_SCRATCH3_DATA_SHIFT 0U
3094 #define ROGUE_CR_OS6_SCRATCH_REPEATCOUNT 2U
3098 #define ROGUE_CR_OS6_SCRATCH0_DATA_SHIFT 0U
3104 #define ROGUE_CR_OS6_SCRATCH1_DATA_SHIFT 0U
3110 #define ROGUE_CR_OS6_SCRATCH2_DATA_SHIFT 0U
3116 #define ROGUE_CR_OS6_SCRATCH3_DATA_SHIFT 0U
3120 #define ROGUE_CR_OS7_SCRATCH_REPEATCOUNT 2U
3124 #define ROGUE_CR_OS7_SCRATCH0_DATA_SHIFT 0U
3130 #define ROGUE_CR_OS7_SCRATCH1_DATA_SHIFT 0U
3136 #define ROGUE_CR_OS7_SCRATCH2_DATA_SHIFT 0U
3142 #define ROGUE_CR_OS7_SCRATCH3_DATA_SHIFT 0U
3148 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_SHIFT 0U
3150 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSHIFT 4U
3151 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSIZE 16U
3156 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_SHIFT 4U
3158 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSHIFT 4U
3159 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSIZE 16U
3162 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEATCOUNT 16U
3166 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_SHIFT 62U
3169 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_SHIFT 61U
3172 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_SHIFT 60U
3175 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT 44U
3177 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT 40U
3179 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_SHIFT 12U
3181 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSHIFT 12U
3182 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSIZE 4096U
3187 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_SHIFT 62U
3190 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_SHIFT 61U
3193 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_SHIFT 60U
3196 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_SHIFT 44U
3198 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_SHIFT 40U
3200 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT 12U
3202 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT 12U
3203 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSIZE 4096U
3208 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_SHIFT 62U
3211 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_SHIFT 61U
3214 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_SHIFT 60U
3217 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_SHIFT 44U
3219 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_SHIFT 40U
3221 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_SHIFT 12U
3223 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSHIFT 12U
3224 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSIZE 4096U
3229 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_SHIFT 62U
3232 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_SHIFT 61U
3235 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_SHIFT 60U
3238 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_SHIFT 44U
3240 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_SHIFT 40U
3242 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_SHIFT 12U
3244 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSHIFT 12U
3245 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSIZE 4096U
3250 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_SHIFT 62U
3253 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_SHIFT 61U
3256 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_SHIFT 60U
3259 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_SHIFT 44U
3261 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_SHIFT 40U
3263 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_SHIFT 12U
3265 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSHIFT 12U
3266 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSIZE 4096U
3271 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_SHIFT 62U
3274 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_SHIFT 61U
3277 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_SHIFT 60U
3280 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_SHIFT 44U
3282 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_SHIFT 40U
3284 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_SHIFT 12U
3286 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSHIFT 12U
3287 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSIZE 4096U
3292 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_SHIFT 62U
3295 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_SHIFT 61U
3298 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_SHIFT 60U
3301 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_SHIFT 44U
3303 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_SHIFT 40U
3305 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_SHIFT 12U
3307 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSHIFT 12U
3308 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSIZE 4096U
3313 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_SHIFT 62U
3316 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_SHIFT 61U
3319 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_SHIFT 60U
3322 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_SHIFT 44U
3324 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_SHIFT 40U
3326 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_SHIFT 12U
3328 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSHIFT 12U
3329 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSIZE 4096U
3334 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_SHIFT 62U
3337 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_SHIFT 61U
3340 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_SHIFT 60U
3343 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_SHIFT 44U
3345 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_SHIFT 40U
3347 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_SHIFT 12U
3349 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSHIFT 12U
3350 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSIZE 4096U
3355 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_SHIFT 62U
3358 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_SHIFT 61U
3361 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_SHIFT 60U
3364 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_SHIFT 44U
3366 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_SHIFT 40U
3368 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_SHIFT 12U
3370 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSHIFT 12U
3371 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSIZE 4096U
3376 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_SHIFT 62U
3379 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_SHIFT 61U
3382 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_SHIFT 60U
3385 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_SHIFT 44U
3387 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_SHIFT 40U
3389 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_SHIFT 12U
3391 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSHIFT 12U
3392 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSIZE 4096U
3397 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_SHIFT 62U
3400 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_SHIFT 61U
3403 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_SHIFT 60U
3406 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_SHIFT 44U
3408 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_SHIFT 40U
3410 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_SHIFT 12U
3412 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSHIFT 12U
3413 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSIZE 4096U
3418 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_SHIFT 62U
3421 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_SHIFT 61U
3424 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_SHIFT 60U
3427 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_SHIFT 44U
3429 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_SHIFT 40U
3431 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_SHIFT 12U
3433 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSHIFT 12U
3434 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSIZE 4096U
3439 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_SHIFT 62U
3442 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_SHIFT 61U
3445 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_SHIFT 60U
3448 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_SHIFT 44U
3450 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_SHIFT 40U
3452 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_SHIFT 12U
3454 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSHIFT 12U
3455 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSIZE 4096U
3460 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_SHIFT 62U
3463 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_SHIFT 61U
3466 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_SHIFT 60U
3469 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_SHIFT 44U
3471 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_SHIFT 40U
3473 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_SHIFT 12U
3475 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSHIFT 12U
3476 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSIZE 4096U
3481 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_SHIFT 62U
3484 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_SHIFT 61U
3487 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_SHIFT 60U
3490 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_SHIFT 44U
3492 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_SHIFT 40U
3494 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_SHIFT 12U
3496 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSHIFT 12U
3497 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSIZE 4096U
3502 #define ROGUE_CR_FWCORE_BOOT_ENABLE_SHIFT 0U
3509 #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_SHIFT 1U
3511 #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSHIFT 1U
3512 #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSIZE 2U
3517 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_SHIFT 1U
3519 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSHIFT 1U
3520 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSIZE 2U
3525 #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_SHIFT 0U
3532 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_SHIFT 12U
3534 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_SHIFT 8U
3536 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_SHIFT 5U
3538 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_SHIFT 4U
3541 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_SHIFT 0U
3548 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_SHIFT 52U
3551 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_SHIFT 46U
3553 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_SHIFT 40U
3555 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_SHIFT 4U
3557 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
3558 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
3563 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_SHIFT 3U
3566 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_SHIFT 2U
3569 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_SHIFT 1U
3572 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_SHIFT 0U
3579 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_SHIFT 20U
3581 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_SHIFT 12U
3583 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_SHIFT 4U
3585 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_SHIFT 2U
3588 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_SHIFT 1U
3591 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_SHIFT 0U
3598 #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_SHIFT 0U
3604 #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_SHIFT 0U
3610 #define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_SHIFT 0U
3615 #define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEATCOUNT 8U
3619 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT 12U
3621 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT 12U
3622 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSIZE 4096U
3627 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_SHIFT 12U
3629 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSHIFT 12U
3630 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSIZE 4096U
3635 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_SHIFT 12U
3637 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSHIFT 12U
3638 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSIZE 4096U
3643 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_SHIFT 12U
3645 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSHIFT 12U
3646 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSIZE 4096U
3651 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_SHIFT 12U
3653 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSHIFT 12U
3654 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSIZE 4096U
3659 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_SHIFT 12U
3661 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSHIFT 12U
3662 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSIZE 4096U
3667 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_SHIFT 12U
3669 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSHIFT 12U
3670 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSIZE 4096U
3675 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_SHIFT 12U
3677 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSHIFT 12U
3678 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSIZE 4096U
3683 #define ROGUE_CR_FWCORE_WDT_RESET_EN_SHIFT 0U
3690 #define ROGUE_CR_FWCORE_WDT_CTRL_PROT_SHIFT 16U
3692 #define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_SHIFT 8U
3694 #define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_SHIFT 0U
3701 #define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_SHIFT 0U
3705 #define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEATCOUNT 4U
3731 #define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEATCOUNT 5U
3761 #define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEATCOUNT 4U
3795 #define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEATCOUNT 2U
3805 #define ROGUE_CR_FWCORE_DMI_SBDATA_REPEATCOUNT 4U
3829 #define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_SHIFT 32U
3831 #define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_SHIFT 24U
3834 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 16U
3842 #define ROGUE_CR_SLC_CTRL_MISC_PAUSE_SHIFT 8U
3845 #define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_SHIFT 3U
3848 #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_SHIFT 2U
3851 #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_SHIFT 1U
3854 #define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_SHIFT 0U
3861 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_SHIFT 31U
3864 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_SHIFT 11U
3867 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_SHIFT 10U
3870 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_SHIFT 9U
3873 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_SHIFT 8U
3876 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_SHIFT 7U
3879 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_SHIFT 6U
3882 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_SHIFT 5U
3885 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_SHIFT 4U
3888 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_SHIFT 3U
3891 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_SHIFT 2U
3894 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_SHIFT 1U
3897 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_SHIFT 0U
3904 #define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_SHIFT 2U
3907 #define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_SHIFT 1U
3910 #define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_SHIFT 0U
3918 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_SHIFT 59U
3921 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_SHIFT 58U
3924 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_SHIFT 57U
3927 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_SHIFT 56U
3930 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_SHIFT 55U
3933 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_SHIFT 54U
3936 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_SHIFT 53U
3939 #define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_SHIFT 52U
3942 #define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_SHIFT 51U
3945 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_SHIFT 50U
3948 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_SHIFT 49U
3951 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_SHIFT 48U
3954 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_SHIFT 47U
3957 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_SHIFT 46U
3960 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_SHIFT 45U
3963 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_SHIFT 44U
3966 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_SHIFT 43U
3969 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_SHIFT 42U
3972 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_SHIFT 41U
3975 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_SHIFT 40U
3978 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_SHIFT 39U
3981 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_SHIFT 38U
3984 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_SHIFT 37U
3987 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_SHIFT 36U
3990 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_SHIFT 35U
3993 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_SHIFT 34U
3996 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_SHIFT 33U
3999 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_SHIFT 32U
4002 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_SHIFT 31U
4005 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_SHIFT 30U
4008 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_SHIFT 29U
4011 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_SHIFT 28U
4014 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_SHIFT 27U
4017 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_SHIFT 26U
4020 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_SHIFT 25U
4023 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_SHIFT 24U
4026 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_SHIFT 23U
4029 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_SHIFT 22U
4032 #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_SHIFT 21U
4035 #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_SHIFT 20U
4038 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_SHIFT 19U
4041 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_SHIFT 18U
4044 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_SHIFT 17U
4047 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_SHIFT 16U
4050 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SHIFT 15U
4053 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_SHIFT 14U
4056 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_SHIFT 13U
4059 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_SHIFT 12U
4062 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_SHIFT 11U
4065 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_SHIFT 10U
4068 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_SHIFT 9U
4071 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_SHIFT 8U
4074 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_SHIFT 7U
4077 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_SHIFT 6U
4080 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_SHIFT 5U
4083 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_SHIFT 4U
4086 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_SHIFT 3U
4089 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_SHIFT 2U
4092 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_SHIFT 1U
4095 #define ROGUE_CR_SLC_CTRL_BYPASS_ALL_SHIFT 0U
4102 #define ROGUE_CR_SLC_STATUS1_PAUSED_SHIFT 63U
4105 #define ROGUE_CR_SLC_STATUS1_READS1_SHIFT 32U
4107 #define ROGUE_CR_SLC_STATUS1_READS0_SHIFT 16U
4109 #define ROGUE_CR_SLC_STATUS1_READS1_EXT_SHIFT 8U
4111 #define ROGUE_CR_SLC_STATUS1_READS0_EXT_SHIFT 0U
4118 #define ROGUE_CR_SLC_IDLE_MH_SYSARB1_SHIFT 9U
4121 #define ROGUE_CR_SLC_IDLE_MH_SYSARB0_SHIFT 8U
4124 #define ROGUE_CR_SLC_IDLE_IMGBV4_SHIFT 7U
4127 #define ROGUE_CR_SLC_IDLE_CACHE_BANKS_SHIFT 6U
4130 #define ROGUE_CR_SLC_IDLE_RBOFIFO_SHIFT 5U
4133 #define ROGUE_CR_SLC_IDLE_FRC_CONV_SHIFT 4U
4136 #define ROGUE_CR_SLC_IDLE_VXE_CONV_SHIFT 3U
4139 #define ROGUE_CR_SLC_IDLE_VXD_CONV_SHIFT 2U
4142 #define ROGUE_CR_SLC_IDLE_BIF1_CONV_SHIFT 1U
4145 #define ROGUE_CR_SLC_IDLE_CBAR_SHIFT 0U
4152 #define ROGUE_CR_SLC_STATUS2_READS3_SHIFT 32U
4154 #define ROGUE_CR_SLC_STATUS2_READS2_SHIFT 16U
4156 #define ROGUE_CR_SLC_STATUS2_READS3_EXT_SHIFT 8U
4158 #define ROGUE_CR_SLC_STATUS2_READS2_EXT_SHIFT 0U
4164 #define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_SHIFT 0U
4170 #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_SHIFT 0U
4177 #define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_SHIFT 0U
4183 #define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_SHIFT 0U
4189 #define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_SHIFT 0U
4195 #define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_SHIFT 0U
4201 #define ROGUE_CR_PPP_SIGNATURE_VALUE_SHIFT 0U
4207 #define ROGUE_CR_TE_SIGNATURE_VALUE_SHIFT 0U
4213 #define ROGUE_CR_TE_CHECKSUM_VALUE_SHIFT 0U
4219 #define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_SHIFT 0U
4225 #define ROGUE_CR_VCE_CHECKSUM_VALUE_SHIFT 0U
4231 #define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_SHIFT 0U
4237 #define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_SHIFT 0U
4243 #define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_SHIFT 0U
4249 #define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_SHIFT 0U
4255 #define ROGUE_CR_PBE_CHECKSUM_VALUE_SHIFT 0U
4261 #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_SHIFT 0U
4267 #define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_SHIFT 0U
4273 #define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_SHIFT 0U
4279 #define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_SHIFT 0U
4285 #define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_SHIFT 0U
4291 #define ROGUE_CR_PERF_TA_PHASE_COUNT_SHIFT 0U
4297 #define ROGUE_CR_PERF_3D_PHASE_COUNT_SHIFT 0U
4303 #define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_SHIFT 0U
4309 #define ROGUE_CR_PERF_TA_CYCLE_COUNT_SHIFT 0U
4315 #define ROGUE_CR_PERF_3D_CYCLE_COUNT_SHIFT 0U
4321 #define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_SHIFT 0U
4327 #define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_SHIFT 0U
4333 #define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_SHIFT 0U
4339 #define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT 0U
4345 #define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT 0U
4351 #define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_SHIFT 0U
4357 #define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_SHIFT 0U
4363 #define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_SHIFT 0U
4369 #define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_SHIFT 0U
4375 #define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_SHIFT 0U
4381 #define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_SHIFT 0U
4387 #define ROGUE_CR_PERF_3D_SPINUP_CYCLES_SHIFT 0U
4393 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_SHIFT 45U
4396 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_SHIFT 37U
4398 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_SHIFT 36U
4403 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_SHIFT 35U
4406 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_SHIFT 34U
4409 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_SHIFT 30U
4411 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_SHIFT 26U
4413 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_SHIFT 22U
4415 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_SHIFT 20U
4417 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_SHIFT 18U
4419 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_SHIFT 16U
4421 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_SHIFT 14U
4423 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_SHIFT 12U
4425 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_SHIFT 10U
4427 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_SHIFT 8U
4429 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_SHIFT 4U
4431 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_SHIFT 0U
4437 #define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_SHIFT 0U
4443 #define ROGUE_CR_TA_PERF_CLR_3_SHIFT 4U
4446 #define ROGUE_CR_TA_PERF_CLR_2_SHIFT 3U
4449 #define ROGUE_CR_TA_PERF_CLR_1_SHIFT 2U
4452 #define ROGUE_CR_TA_PERF_CLR_0_SHIFT 1U
4455 #define ROGUE_CR_TA_PERF_CTRL_ENABLE_SHIFT 0U
4462 #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4464 #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4466 #define ROGUE_CR_TA_PERF_SELECT0_MODE_SHIFT 21U
4469 #define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4471 #define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4477 #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_SHIFT 48U
4479 #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_SHIFT 32U
4481 #define ROGUE_CR_TA_PERF_SELECT1_MODE_SHIFT 21U
4484 #define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_SHIFT 16U
4486 #define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_SHIFT 0U
4492 #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_SHIFT 48U
4494 #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_SHIFT 32U
4496 #define ROGUE_CR_TA_PERF_SELECT2_MODE_SHIFT 21U
4499 #define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_SHIFT 16U
4501 #define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_SHIFT 0U
4507 #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_SHIFT 48U
4509 #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_SHIFT 32U
4511 #define ROGUE_CR_TA_PERF_SELECT3_MODE_SHIFT 21U
4514 #define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_SHIFT 16U
4516 #define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_SHIFT 0U
4522 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_SHIFT 48U
4524 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_SHIFT 32U
4526 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_SHIFT 16U
4528 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_SHIFT 0U
4534 #define ROGUE_CR_TA_PERF_COUNTER_0_REG_SHIFT 0U
4540 #define ROGUE_CR_TA_PERF_COUNTER_1_REG_SHIFT 0U
4546 #define ROGUE_CR_TA_PERF_COUNTER_2_REG_SHIFT 0U
4552 #define ROGUE_CR_TA_PERF_COUNTER_3_REG_SHIFT 0U
4558 #define ROGUE_CR_RASTERISATION_PERF_CLR_3_SHIFT 4U
4561 #define ROGUE_CR_RASTERISATION_PERF_CLR_2_SHIFT 3U
4564 #define ROGUE_CR_RASTERISATION_PERF_CLR_1_SHIFT 2U
4567 #define ROGUE_CR_RASTERISATION_PERF_CLR_0_SHIFT 1U
4570 #define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_SHIFT 0U
4577 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4579 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4581 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_SHIFT 21U
4584 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4586 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4592 #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_SHIFT 0U
4598 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_SHIFT 4U
4601 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_SHIFT 3U
4604 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_SHIFT 2U
4607 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_SHIFT 1U
4610 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_SHIFT 0U
4617 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4619 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4621 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_SHIFT 21U
4624 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4626 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4632 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_SHIFT 0U
4638 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_SHIFT 4U
4641 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_SHIFT 3U
4644 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_SHIFT 2U
4647 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_SHIFT 1U
4650 #define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_SHIFT 0U
4657 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4659 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4661 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_SHIFT 21U
4664 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4666 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4672 #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_SHIFT 0U
4678 #define ROGUE_CR_USC_PERF_CLR_3_SHIFT 4U
4681 #define ROGUE_CR_USC_PERF_CLR_2_SHIFT 3U
4684 #define ROGUE_CR_USC_PERF_CLR_1_SHIFT 2U
4687 #define ROGUE_CR_USC_PERF_CLR_0_SHIFT 1U
4690 #define ROGUE_CR_USC_PERF_CTRL_ENABLE_SHIFT 0U
4697 #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4699 #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4701 #define ROGUE_CR_USC_PERF_SELECT0_MODE_SHIFT 21U
4704 #define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4706 #define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4712 #define ROGUE_CR_USC_PERF_COUNTER_0_REG_SHIFT 0U
4718 #define ROGUE_CR_JONES_IDLE_TDM_SHIFT 14U
4721 #define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_SHIFT 13U
4724 #define ROGUE_CR_JONES_IDLE_FB_CDC_SHIFT 12U
4727 #define ROGUE_CR_JONES_IDLE_MMU_SHIFT 11U
4730 #define ROGUE_CR_JONES_IDLE_TLA_SHIFT 10U
4733 #define ROGUE_CR_JONES_IDLE_GARTEN_SHIFT 9U
4736 #define ROGUE_CR_JONES_IDLE_HOSTIF_SHIFT 8U
4739 #define ROGUE_CR_JONES_IDLE_SOCIF_SHIFT 7U
4742 #define ROGUE_CR_JONES_IDLE_TILING_SHIFT 6U
4745 #define ROGUE_CR_JONES_IDLE_IPP_SHIFT 5U
4748 #define ROGUE_CR_JONES_IDLE_USCS_SHIFT 4U
4751 #define ROGUE_CR_JONES_IDLE_PM_SHIFT 3U
4754 #define ROGUE_CR_JONES_IDLE_CDM_SHIFT 2U
4757 #define ROGUE_CR_JONES_IDLE_VDM_SHIFT 1U
4760 #define ROGUE_CR_JONES_IDLE_BIF_SHIFT 0U
4767 #define ROGUE_CR_TORNADO_PERF_CLR_3_SHIFT 4U
4770 #define ROGUE_CR_TORNADO_PERF_CLR_2_SHIFT 3U
4773 #define ROGUE_CR_TORNADO_PERF_CLR_1_SHIFT 2U
4776 #define ROGUE_CR_TORNADO_PERF_CLR_0_SHIFT 1U
4779 #define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_SHIFT 0U
4786 #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4788 #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4790 #define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_SHIFT 21U
4793 #define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4795 #define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4801 #define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_SHIFT 0U
4807 #define ROGUE_CR_TEXAS_PERF_CLR_5_SHIFT 6U
4810 #define ROGUE_CR_TEXAS_PERF_CLR_4_SHIFT 5U
4813 #define ROGUE_CR_TEXAS_PERF_CLR_3_SHIFT 4U
4816 #define ROGUE_CR_TEXAS_PERF_CLR_2_SHIFT 3U
4819 #define ROGUE_CR_TEXAS_PERF_CLR_1_SHIFT 2U
4822 #define ROGUE_CR_TEXAS_PERF_CLR_0_SHIFT 1U
4825 #define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_SHIFT 0U
4832 #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4834 #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4836 #define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_SHIFT 31U
4839 #define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4841 #define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4847 #define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_SHIFT 0U
4853 #define ROGUE_CR_JONES_PERF_CLR_3_SHIFT 4U
4856 #define ROGUE_CR_JONES_PERF_CLR_2_SHIFT 3U
4859 #define ROGUE_CR_JONES_PERF_CLR_1_SHIFT 2U
4862 #define ROGUE_CR_JONES_PERF_CLR_0_SHIFT 1U
4865 #define ROGUE_CR_JONES_PERF_CTRL_ENABLE_SHIFT 0U
4872 #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4874 #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4876 #define ROGUE_CR_JONES_PERF_SELECT0_MODE_SHIFT 21U
4879 #define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4881 #define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4887 #define ROGUE_CR_JONES_PERF_COUNTER_0_REG_SHIFT 0U
4893 #define ROGUE_CR_BLACKPEARL_PERF_CLR_5_SHIFT 6U
4896 #define ROGUE_CR_BLACKPEARL_PERF_CLR_4_SHIFT 5U
4899 #define ROGUE_CR_BLACKPEARL_PERF_CLR_3_SHIFT 4U
4902 #define ROGUE_CR_BLACKPEARL_PERF_CLR_2_SHIFT 3U
4905 #define ROGUE_CR_BLACKPEARL_PERF_CLR_1_SHIFT 2U
4908 #define ROGUE_CR_BLACKPEARL_PERF_CLR_0_SHIFT 1U
4911 #define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_SHIFT 0U
4918 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4920 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4922 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_SHIFT 31U
4925 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4927 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4933 #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_SHIFT 0U
4939 #define ROGUE_CR_PBE_PERF_CLR_3_SHIFT 4U
4942 #define ROGUE_CR_PBE_PERF_CLR_2_SHIFT 3U
4945 #define ROGUE_CR_PBE_PERF_CLR_1_SHIFT 2U
4948 #define ROGUE_CR_PBE_PERF_CLR_0_SHIFT 1U
4951 #define ROGUE_CR_PBE_PERF_CTRL_ENABLE_SHIFT 0U
4958 #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4960 #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4962 #define ROGUE_CR_PBE_PERF_SELECT0_MODE_SHIFT 21U
4965 #define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4967 #define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4973 #define ROGUE_CR_PBE_PERF_COUNTER_0_REG_SHIFT 0U
4979 #define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_SHIFT 33U
4981 #define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_SHIFT 32U
4984 #define ROGUE_CR_OCP_REVINFO_REVISION_SHIFT 0U
4990 #define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_SHIFT 10U
4992 #define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_SHIFT 8U
4994 #define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_SHIFT 6U
4996 #define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_SHIFT 4U
4998 #define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_SHIFT 2U
5000 #define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_SHIFT 0U
5006 #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_SHIFT 0U
5013 #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_SHIFT 0U
5020 #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_SHIFT 0U
5027 #define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_SHIFT 0U
5034 #define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_SHIFT 0U
5041 #define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_SHIFT 0U
5048 #define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_SHIFT 0U
5055 #define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_SHIFT 0U
5062 #define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_SHIFT 0U
5069 #define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_SHIFT 0U
5076 #define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_SHIFT 0U
5083 #define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_SHIFT 0U
5090 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_SHIFT 19U
5093 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_SHIFT 18U
5096 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_SHIFT 17U
5099 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_SHIFT 16U
5102 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_SHIFT 15U
5105 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_SHIFT 14U
5108 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_SHIFT 13U
5111 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_SHIFT 12U
5114 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_SHIFT 11U
5117 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_SHIFT 10U
5120 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_SHIFT 9U
5123 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_SHIFT 8U
5126 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_SHIFT 7U
5129 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_SHIFT 6U
5132 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_SHIFT 5U
5135 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_SHIFT 4U
5138 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_SHIFT 3U
5141 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_SHIFT 2U
5144 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_SHIFT 1U
5147 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_SHIFT 0U
5154 #define ROGUE_CR_OCP_DEBUG_CONFIG_REG_SHIFT 0U
5161 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_SHIFT 51U
5163 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_SHIFT 50U
5166 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_SHIFT 48U
5168 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_SHIFT 43U
5170 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_SHIFT 42U
5173 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_SHIFT 40U
5175 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_SHIFT 38U
5178 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_SHIFT 37U
5181 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_SHIFT 36U
5184 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_SHIFT 34U
5187 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_SHIFT 33U
5190 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_SHIFT 32U
5193 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_SHIFT 31U
5196 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_SHIFT 30U
5199 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_SHIFT 29U
5202 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_SHIFT 27U
5204 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_SHIFT 26U
5207 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_SHIFT 24U
5209 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_SHIFT 23U
5212 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_SHIFT 22U
5215 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_SHIFT 21U
5218 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_SHIFT 19U
5220 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_SHIFT 18U
5223 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_SHIFT 16U
5225 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_SHIFT 15U
5228 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_SHIFT 14U
5231 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_SHIFT 13U
5234 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_SHIFT 11U
5236 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_SHIFT 10U
5239 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_SHIFT 8U
5241 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_SHIFT 7U
5244 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_SHIFT 6U
5247 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_SHIFT 5U
5250 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_SHIFT 3U
5252 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_SHIFT 2U
5255 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_SHIFT 0U
5258 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_SHIFT 6U
5261 #define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_SHIFT 5U
5264 #define ROGUE_CR_BIF_TRUST_DM_TYPE_META_SHIFT 4U
5267 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_SHIFT 3U
5270 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_SHIFT 2U
5273 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_SHIFT 1U
5276 #define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_SHIFT 0U
5285 #define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_SHIFT 20U
5288 #define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_SHIFT 19U
5291 #define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_SHIFT 18U
5294 #define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_SHIFT 17U
5297 #define ROGUE_CR_BIF_TRUST_ENABLE_SHIFT 16U
5300 #define ROGUE_CR_BIF_TRUST_DM_TRUSTED_SHIFT 9U
5302 #define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_SHIFT 8U
5305 #define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_SHIFT 7U
5308 #define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_SHIFT 6U
5311 #define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_SHIFT 5U
5314 #define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_SHIFT 4U
5317 #define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_SHIFT 3U
5320 #define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_SHIFT 2U
5323 #define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_SHIFT 1U
5326 #define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_SHIFT 0U
5334 #define ROGUE_CR_SYS_BUS_SECURE_ENABLE_SHIFT 0U
5341 #define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_SHIFT 0U
5347 #define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_SHIFT 0U
5353 #define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_SHIFT 0U
5359 #define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_SHIFT 0U
5365 #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_SHIFT 10U
5370 #define ROGUE_CR_CLK_CTRL2_VRDM_SHIFT 8U
5375 #define ROGUE_CR_CLK_CTRL2_SH_SHIFT 4U
5380 #define ROGUE_CR_CLK_CTRL2_FBA_SHIFT 0U
5389 #define ROGUE_CR_CLK_STATUS2_VRDM_SHIFT 4U
5393 #define ROGUE_CR_CLK_STATUS2_SH_SHIFT 2U
5397 #define ROGUE_CR_CLK_STATUS2_FBA_SHIFT 0U
5405 #define ROGUE_CR_RPM_SHF_FPL_SIZE_SHIFT 40U
5407 #define ROGUE_CR_RPM_SHF_FPL_BASE_SHIFT 2U
5409 #define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSHIFT 2U
5410 #define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSIZE 4U
5415 #define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_SHIFT 22U
5418 #define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_SHIFT 0U
5424 #define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_SHIFT 22U
5427 #define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_SHIFT 0U
5433 #define ROGUE_CR_RPM_SHG_FPL_SIZE_SHIFT 40U
5435 #define ROGUE_CR_RPM_SHG_FPL_BASE_SHIFT 2U
5437 #define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSHIFT 2U
5438 #define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSIZE 4U
5443 #define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_SHIFT 22U
5446 #define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_SHIFT 0U
5452 #define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_SHIFT 22U
5455 #define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_SHIFT 0U
5461 #define ROGUE_CR_SH_PERF_CLR_3_SHIFT 4U
5464 #define ROGUE_CR_SH_PERF_CLR_2_SHIFT 3U
5467 #define ROGUE_CR_SH_PERF_CLR_1_SHIFT 2U
5470 #define ROGUE_CR_SH_PERF_CLR_0_SHIFT 1U
5473 #define ROGUE_CR_SH_PERF_CTRL_ENABLE_SHIFT 0U
5480 #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5482 #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5484 #define ROGUE_CR_SH_PERF_SELECT0_MODE_SHIFT 21U
5487 #define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5489 #define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5495 #define ROGUE_CR_SH_PERF_COUNTER_0_REG_SHIFT 0U
5501 #define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_SHIFT 0U
5507 #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_SHIFT 0U
5513 #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_SHIFT 0U
5519 #define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_SHIFT 0U
5525 #define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_SHIFT 0U
5531 #define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_SHIFT 0U
5537 #define DPX_CR_BF_PERF_CLR_3_SHIFT 4U
5540 #define DPX_CR_BF_PERF_CLR_2_SHIFT 3U
5543 #define DPX_CR_BF_PERF_CLR_1_SHIFT 2U
5546 #define DPX_CR_BF_PERF_CLR_0_SHIFT 1U
5549 #define DPX_CR_BF_PERF_CTRL_ENABLE_SHIFT 0U
5556 #define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5558 #define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5560 #define DPX_CR_BF_PERF_SELECT0_MODE_SHIFT 21U
5563 #define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5565 #define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5571 #define DPX_CR_BF_PERF_COUNTER_0_REG_SHIFT 0U
5577 #define DPX_CR_BT_PERF_CLR_3_SHIFT 4U
5580 #define DPX_CR_BT_PERF_CLR_2_SHIFT 3U
5583 #define DPX_CR_BT_PERF_CLR_1_SHIFT 2U
5586 #define DPX_CR_BT_PERF_CLR_0_SHIFT 1U
5589 #define DPX_CR_BT_PERF_CTRL_ENABLE_SHIFT 0U
5596 #define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5598 #define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5600 #define DPX_CR_BT_PERF_SELECT0_MODE_SHIFT 21U
5603 #define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5605 #define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5611 #define DPX_CR_BT_PERF_COUNTER_0_REG_SHIFT 0U
5617 #define DPX_CR_RQ_USC_DEBUG_CHECKSUM_SHIFT 0U
5623 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_SHIFT 12U
5625 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_SHIFT 8U
5627 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_SHIFT 5U
5629 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_SHIFT 4U
5632 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
5635 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_SHIFT 0U
5642 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_SHIFT 57U
5645 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_SHIFT 44U
5647 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_SHIFT 40U
5649 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_SHIFT 4U
5651 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
5652 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
5657 #define DPX_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U
5659 #define DPX_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U
5661 #define DPX_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U
5663 #define DPX_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U
5666 #define DPX_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U
5669 #define DPX_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U
5676 #define DPX_CR_RT_PERF_CLR_3_SHIFT 4U
5679 #define DPX_CR_RT_PERF_CLR_2_SHIFT 3U
5682 #define DPX_CR_RT_PERF_CLR_1_SHIFT 2U
5685 #define DPX_CR_RT_PERF_CLR_0_SHIFT 1U
5688 #define DPX_CR_RT_PERF_CTRL_ENABLE_SHIFT 0U
5695 #define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5697 #define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5699 #define DPX_CR_RT_PERF_SELECT0_MODE_SHIFT 21U
5702 #define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5704 #define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5710 #define DPX_CR_RT_PERF_COUNTER_0_REG_SHIFT 0U
5716 #define DPX_CR_BX_TU_PERF_CLR_3_SHIFT 4U
5719 #define DPX_CR_BX_TU_PERF_CLR_2_SHIFT 3U
5722 #define DPX_CR_BX_TU_PERF_CLR_1_SHIFT 2U
5725 #define DPX_CR_BX_TU_PERF_CLR_0_SHIFT 1U
5728 #define DPX_CR_BX_TU_PERF_CTRL_ENABLE_SHIFT 0U
5735 #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5737 #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5739 #define DPX_CR_BX_TU_PERF_SELECT0_MODE_SHIFT 21U
5742 #define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5744 #define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5750 #define DPX_CR_BX_TU_PERF_COUNTER_0_REG_SHIFT 0U
5756 #define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_SHIFT 0U
5762 #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT 0U
5768 #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT 0U
5770 #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT 12U
5771 #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE 4096U
5776 #define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_SHIFT 28U
5778 #define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_SHIFT 20U
5780 #define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_SHIFT 12U
5782 #define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_SHIFT 6U
5784 #define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_SHIFT 4U
5786 #define ROGUE_CR_MMU_FAULT_STATUS_RNW_SHIFT 3U
5789 #define ROGUE_CR_MMU_FAULT_STATUS_TYPE_SHIFT 1U
5791 #define ROGUE_CR_MMU_FAULT_STATUS_FAULT_SHIFT 0U
5798 #define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT 28U
5800 #define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT 20U
5802 #define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_SHIFT 12U
5804 #define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT 6U
5806 #define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT 4U
5808 #define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_SHIFT 3U
5811 #define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT 1U
5813 #define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT 0U
5820 #define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_SHIFT 8U
5823 #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 0U
5834 #define ROGUE_CR_SLC3_SCRAMBLE_BITS_SHIFT 0U
5840 #define ROGUE_CR_SLC3_SCRAMBLE2_BITS_SHIFT 0U
5846 #define ROGUE_CR_SLC3_SCRAMBLE3_BITS_SHIFT 0U
5852 #define ROGUE_CR_SLC3_SCRAMBLE4_BITS_SHIFT 0U
5858 #define ROGUE_CR_SLC3_STATUS_WRITES1_SHIFT 48U
5860 #define ROGUE_CR_SLC3_STATUS_WRITES0_SHIFT 32U
5862 #define ROGUE_CR_SLC3_STATUS_READS1_SHIFT 16U
5864 #define ROGUE_CR_SLC3_STATUS_READS0_SHIFT 0U
5870 #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_SHIFT 18U
5872 #define ROGUE_CR_SLC3_IDLE_MMU_SHIFT 17U
5875 #define ROGUE_CR_SLC3_IDLE_RDI_SHIFT 16U
5878 #define ROGUE_CR_SLC3_IDLE_IMGBV4_SHIFT 12U
5880 #define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_SHIFT 4U
5882 #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_SHIFT 2U
5884 #define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_SHIFT 1U
5887 #define ROGUE_CR_SLC3_IDLE_XBAR_SHIFT 0U
5894 #define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_SHIFT 0U
5900 #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_SHIFT 0U
5909 #define ROGUE_CR_CONTEXT_MAPPING0_2D_SHIFT 24U
5911 #define ROGUE_CR_CONTEXT_MAPPING0_CDM_SHIFT 16U
5913 #define ROGUE_CR_CONTEXT_MAPPING0_3D_SHIFT 8U
5915 #define ROGUE_CR_CONTEXT_MAPPING0_TA_SHIFT 0U
5921 #define ROGUE_CR_CONTEXT_MAPPING1_HOST_SHIFT 8U
5923 #define ROGUE_CR_CONTEXT_MAPPING1_TLA_SHIFT 0U
5929 #define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_SHIFT 16U
5931 #define ROGUE_CR_CONTEXT_MAPPING2_TE0_SHIFT 8U
5933 #define ROGUE_CR_CONTEXT_MAPPING2_VCE0_SHIFT 0U
5939 #define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_SHIFT 16U
5941 #define ROGUE_CR_CONTEXT_MAPPING3_TE1_SHIFT 8U
5943 #define ROGUE_CR_CONTEXT_MAPPING3_VCE1_SHIFT 0U
5949 #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_SHIFT 0U
5955 #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_SHIFT 0U
5961 #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_SHIFT 0U
5967 #define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_SHIFT 40U
5969 #define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_SHIFT 32U
5971 #define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_SHIFT 24U
5973 #define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_SHIFT 16U
5975 #define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_SHIFT 8U
5977 #define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_SHIFT 0U
5983 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_SHIFT 6U
5986 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_SHIFT 5U
5989 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_SHIFT 4U
5992 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_SHIFT 3U
5995 #define ROGUE_CR_MULTICORE_GPU_ID_SHIFT 0U
6001 #define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_SHIFT 0U
6007 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
6009 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
6011 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
6017 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
6019 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
6021 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
6027 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
6029 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
6031 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
6037 #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U
6040 #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U
6043 #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U
6046 #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U
6049 #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U
6056 #define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_SHIFT 4U
6059 #define ROGUE_CR_ECC_RAM_INIT_KICK_USC_SHIFT 3U
6062 #define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_SHIFT 2U
6065 #define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_SHIFT 1U
6068 #define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_SHIFT 0U
6075 #define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_SHIFT 4U
6078 #define ROGUE_CR_ECC_RAM_INIT_DONE_USC_SHIFT 3U
6081 #define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_SHIFT 2U
6084 #define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_SHIFT 1U
6087 #define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_SHIFT 0U
6094 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
6097 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
6100 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
6103 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U
6106 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U
6109 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U
6112 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
6119 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
6122 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
6125 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
6128 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_SHIFT 3U
6131 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_SHIFT 2U
6134 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_SHIFT 1U
6137 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
6144 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
6147 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
6150 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
6153 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_SHIFT 3U
6156 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_SHIFT 2U
6159 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_SHIFT 1U
6162 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
6169 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
6172 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
6175 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
6178 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U
6181 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U
6184 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U
6187 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U