Lines Matching full:default
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
19 * Default 1.
22 * Default 1.
24 * Default 1.
26 * 0=Release from reset. Default 1.
28 * 0=Release from reset. Default 1.
34 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
35 * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
36 * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
37 * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
38 * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
42 * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A
43 * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
44 * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
45 * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0.
46 * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0.
53 * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0.
54 * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0.
60 * 1=Enable interrupt source; 0=Disable interrupt source. Default 0.
105 * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
107 * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
109 * Default 0.
110 * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0.
112 * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
113 * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.
117 /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */
118 /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */
119 /* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */
122 /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */
123 /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */
124 /* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */
127 /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */
128 /* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */
131 /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */
132 /* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */
135 /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */
136 /* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
141 * used when TMDS CLK rate = TMDS character rate /4. Default 0.
142 * Bit 0 R Reserved. Default 0.
150 * failure, write 1 to clear the failure flag. Default 0.