35  * These define the different GMU wake up options - these define how both the
36  * CPU and the GMU bring up the hardware
39 /* THe GMU has already been booted and the rentention registers are active */
42 /* the GMU is coming up for the first time or back from a power collapse */
46  * These define the level of control that the GMU has - the higher the number
47  * the more things that the GMU hardware controls on its own.
50 /* The GMU does not do any idle state management */
53 /* The GMU manages SPTP power collapse */
56 /* The GMU does automatic IFPC (intra-frame power collapse) */
62 	/* For serializing communication with the GMU: */
121 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)  in gmu_read()  argument
123 	return readl(gmu->mmio + (offset << 2));  in gmu_read()
126 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)  in gmu_write()  argument
128 	writel(value, gmu->mmio + (offset << 2));  in gmu_write()
132 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)  in gmu_write_bulk()  argument
134 	memcpy_toio(gmu->mmio + (offset << 2), data, size);  in gmu_write_bulk()
138 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)  in gmu_rmw()  argument
140 	u32 val = gmu_read(gmu, reg);  in gmu_rmw()
144 	gmu_write(gmu, reg, val | or);  in gmu_rmw()
147 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)  in gmu_read64()  argument
151 	val = (u64) readl(gmu->mmio + (lo << 2));  in gmu_read64()
152 	val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);  in gmu_read64()
157 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \  argument
158 	readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
161 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)  in gmu_read_rscc()  argument
163 	return readl(gmu->rscc + (offset << 2));  in gmu_read_rscc()
166 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)  in gmu_write_rscc()  argument
168 	writel(value, gmu->rscc + (offset << 2));  in gmu_write_rscc()
171 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \  argument
172 	readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
176  * These are the available OOB (out of band requests) to the GMU where "out of
177  * band" means that the CPU talks to the GMU directly and not through HFI.
180  * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
182  * These are used to force the GMU/GPU to stay on during a critical sequence or
188 	 * Let the GMU know that a boot or slumber operation has started. The value in
189 	 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
194 	 * Let the GMU know to not turn off any GPU registers while the CPU is in a
208 void a6xx_hfi_init(struct a6xx_gmu *gmu);
209 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
210 void a6xx_hfi_stop(struct a6xx_gmu *gmu);
211 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
212 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 perf_index, u32 bw_index);
214 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
215 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
216 void a6xx_sptprac_disable(struct a6xx_gmu *gmu);
217 int a6xx_sptprac_enable(struct a6xx_gmu *gmu);