29 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &  in _a6xx_check_idle()
33 	return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &  in _a6xx_check_idle()
46 			gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_idle()
47 			gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),  in a6xx_idle()
48 			gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_idle()
49 			gpu_read(gpu, REG_A6XX_CP_RB_WPTR));  in a6xx_idle()
543 	val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);  in a6xx_set_hwcg()
727 		*dest++ = gpu_read(gpu, reglist->regs[i]);  in a7xx_patch_pwrup_reglist()
1056 		gpu_read(gpu, REG_A6XX_GBIF_HALT);  in hw_init()
1059 		gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL);  in hw_init()
1062 		gpu_read(gpu, REG_A6XX_GBIF_HALT);  in hw_init()
1065 		gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT);  in hw_init()
1411 			gpu_read(gpu, REG_A6XX_RBBM_STATUS));  in a6xx_dump()
1426 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));  in a6xx_recover()
1511 	val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);  in a6xx_uche_fault_block()
1613 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),  in a6xx_fault_handler()
1614 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),  in a6xx_fault_handler()
1615 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),  in a6xx_fault_handler()
1616 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)),  in a6xx_fault_handler()
1627 	u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);  in a6xx_cp_hw_err_irq()
1633 		val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);  in a6xx_cp_hw_err_irq()
1645 			gpu_read(gpu, REG_A6XX_CP_HW_FAULT));  in a6xx_cp_hw_err_irq()
1648 		u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);  in a6xx_cp_hw_err_irq()
1679 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)  in a6xx_fault_detect_irq()
1692 		gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_fault_detect_irq()
1693 		gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_fault_detect_irq()
1694 		gpu_read(gpu, REG_A6XX_CP_RB_WPTR),  in a6xx_fault_detect_irq()
1696 		gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),  in a6xx_fault_detect_irq()
1698 		gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));  in a6xx_fault_detect_irq()
1710 	status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);  in a7xx_sw_fuse_violation_irq()
1730 	u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);  in a6xx_irq()
1966 		spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) &  in a6xx_bus_clear_pending_transactions()
1970 		spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &  in a6xx_bus_clear_pending_transactions()
1980 		spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);  in a6xx_bus_clear_pending_transactions()
1985 	spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &  in a6xx_bus_clear_pending_transactions()
1990 	spin_until((gpu_read(gpu,  REG_A6XX_GBIF_HALT_ACK) &  in a6xx_bus_clear_pending_transactions()
2005 	gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD);  in a6xx_gpu_sw_reset()
2275 	return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);  in a6xx_get_rptr()
2283 		.ib1_rem  = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),  in a6xx_progress()
2284 		.ib2_rem  = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE),  in a6xx_progress()
2301 	cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16;  in a6xx_progress()
2302 	cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16;  in a6xx_progress()