29 static inline void set_preempt_state(struct a6xx_gpu *gpu,  in set_preempt_state()  argument
38 	atomic_set(&gpu->preempt_state, new);  in set_preempt_state()
44 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in update_wptr()  argument
54 		gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);  in update_wptr()
63 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu)  in get_next_ring()  argument
65 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in get_next_ring()
71 	for (i = 0; i < gpu->nr_rings; i++) {  in get_next_ring()
73 		struct msm_ringbuffer *ring = gpu->rb[i];  in get_next_ring()
76 		empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring));  in get_next_ring()
91 	struct msm_gpu *gpu = &a6xx_gpu->base.base;  in a6xx_preempt_timer()  local
92 	struct drm_device *dev = gpu->dev;  in a6xx_preempt_timer()
97 	dev_err(dev->dev, "%s: preemption timed out\n", gpu->name);  in a6xx_preempt_timer()
98 	kthread_queue_work(gpu->worker, &gpu->recover_work);  in a6xx_preempt_timer()
138 void a6xx_preempt_irq(struct msm_gpu *gpu)  in a6xx_preempt_irq()  argument
141 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_irq()
143 	struct drm_device *dev = gpu->dev;  in a6xx_preempt_irq()
158 	status = gpu_read(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL);  in a6xx_preempt_irq()
160 		DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_preempt_irq()
164 			gpu->name);  in a6xx_preempt_irq()
165 		kthread_queue_work(gpu->worker, &gpu->recover_work);  in a6xx_preempt_irq()
174 	update_wptr(gpu, a6xx_gpu->cur_ring);  in a6xx_preempt_irq()
184 	a6xx_preempt_trigger(gpu);  in a6xx_preempt_irq()
187 void a6xx_preempt_hw_init(struct msm_gpu *gpu)  in a6xx_preempt_hw_init()  argument
189 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_hw_init()
194 	if (gpu->nr_rings == 1)  in a6xx_preempt_hw_init()
197 	for (i = 0; i < gpu->nr_rings; i++) {  in a6xx_preempt_hw_init()
202 		record_ptr->rptr_addr = shadowptr(a6xx_gpu, gpu->rb[i]);  in a6xx_preempt_hw_init()
205 		record_ptr->rbase = gpu->rb[i]->iova;  in a6xx_preempt_hw_init()
209 	gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0);  in a6xx_preempt_hw_init()
212 	gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x1);  in a6xx_preempt_hw_init()
220 	a6xx_gpu->cur_ring = gpu->rb[0];  in a6xx_preempt_hw_init()
223 void a6xx_preempt_trigger(struct msm_gpu *gpu)  in a6xx_preempt_trigger()  argument
225 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_trigger()
232 	if (gpu->nr_rings == 1)  in a6xx_preempt_trigger()
262 	ring = get_next_ring(gpu);  in a6xx_preempt_trigger()
270 		update_wptr(gpu, a6xx_gpu->cur_ring);  in a6xx_preempt_trigger()
291 	 * The GPU will write the wptr we set above when we preempt. Reset  in a6xx_preempt_trigger()
304 	gpu_write64(gpu,  in a6xx_preempt_trigger()
308 	gpu_write64(gpu,  in a6xx_preempt_trigger()
330 	gpu_write(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl);  in a6xx_preempt_trigger()
337 	struct msm_gpu *gpu = &adreno_gpu->base;  in preempt_init_ring()  local
344 	ptr = msm_gem_kernel_new(gpu->dev,  in preempt_init_ring()
346 		MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);  in preempt_init_ring()
361 	ptr = msm_gem_kernel_new(gpu->dev,  in preempt_init_ring()
364 		gpu->aspace, &bo, &iova);  in preempt_init_ring()
379 	msm_iommu_pagetable_params(gpu->aspace->mmu, &ttbr, &asid);  in preempt_init_ring()
400 void a6xx_preempt_fini(struct msm_gpu *gpu)  in a6xx_preempt_fini()  argument
402 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_fini()
406 	for (i = 0; i < gpu->nr_rings; i++)  in a6xx_preempt_fini()
407 		msm_gem_kernel_put(a6xx_gpu->preempt_bo[i], gpu->aspace);  in a6xx_preempt_fini()
410 void a6xx_preempt_init(struct msm_gpu *gpu)  in a6xx_preempt_init()  argument
412 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_init()
417 	if (gpu->nr_rings <= 1)  in a6xx_preempt_init()
420 	for (i = 0; i < gpu->nr_rings; i++) {  in a6xx_preempt_init()
421 		if (preempt_init_ring(a6xx_gpu, gpu->rb[i]))  in a6xx_preempt_init()
430 	a6xx_gpu->preempt_postamble_ptr  = msm_gem_kernel_new(gpu->dev,  in a6xx_preempt_init()
433 			gpu->aspace, &a6xx_gpu->preempt_postamble_bo,  in a6xx_preempt_init()
449 	a6xx_preempt_fini(gpu);  in a6xx_preempt_init()
450 	gpu->nr_rings = 1;  in a6xx_preempt_init()
452 	DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_preempt_init()