Lines Matching full:cfg
283 struct hdmi_8998_phy_pll_reg_cfg *cfg) in pll_calculate() argument
330 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
332 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
334 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
335 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
336 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
337 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
338 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
339 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
340 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
341 cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16); in pll_calculate()
342 cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xff); in pll_calculate()
343 cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8); in pll_calculate()
344 cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xff); in pll_calculate()
345 cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xff00) >> 8); in pll_calculate()
346 cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); in pll_calculate()
347 cfg->com_lock_cmp_en = 0x0; in pll_calculate()
348 cfg->com_core_clk_en = 0x2c; in pll_calculate()
349 cfg->com_coreclk_div_mode0 = HDMI_CORECLK_DIV; in pll_calculate()
350 cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x5 : 0x4; in pll_calculate()
353 cfg->tx_lx_tx_band[i] = pd.tx_band_sel; in pll_calculate()
356 cfg->tx_lx_tx_drv_lvl[0] = 0x0f; in pll_calculate()
357 cfg->tx_lx_tx_drv_lvl[1] = 0x0f; in pll_calculate()
358 cfg->tx_lx_tx_drv_lvl[2] = 0x0f; in pll_calculate()
359 cfg->tx_lx_tx_drv_lvl[3] = 0x0f; in pll_calculate()
360 cfg->tx_lx_tx_emp_post1_lvl[0] = 0x03; in pll_calculate()
361 cfg->tx_lx_tx_emp_post1_lvl[1] = 0x02; in pll_calculate()
362 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x03; in pll_calculate()
363 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00; in pll_calculate()
364 cfg->tx_lx_pre_driver_1[0] = 0x00; in pll_calculate()
365 cfg->tx_lx_pre_driver_1[1] = 0x00; in pll_calculate()
366 cfg->tx_lx_pre_driver_1[2] = 0x00; in pll_calculate()
367 cfg->tx_lx_pre_driver_1[3] = 0x00; in pll_calculate()
368 cfg->tx_lx_pre_driver_2[0] = 0x1C; in pll_calculate()
369 cfg->tx_lx_pre_driver_2[1] = 0x1C; in pll_calculate()
370 cfg->tx_lx_pre_driver_2[2] = 0x1C; in pll_calculate()
371 cfg->tx_lx_pre_driver_2[3] = 0x00; in pll_calculate()
372 cfg->tx_lx_res_code_offset[0] = 0x03; in pll_calculate()
373 cfg->tx_lx_res_code_offset[1] = 0x00; in pll_calculate()
374 cfg->tx_lx_res_code_offset[2] = 0x00; in pll_calculate()
375 cfg->tx_lx_res_code_offset[3] = 0x03; in pll_calculate()
377 cfg->tx_lx_tx_drv_lvl[0] = 0x0f; in pll_calculate()
378 cfg->tx_lx_tx_drv_lvl[1] = 0x0f; in pll_calculate()
379 cfg->tx_lx_tx_drv_lvl[2] = 0x0f; in pll_calculate()
380 cfg->tx_lx_tx_drv_lvl[3] = 0x0f; in pll_calculate()
381 cfg->tx_lx_tx_emp_post1_lvl[0] = 0x03; in pll_calculate()
382 cfg->tx_lx_tx_emp_post1_lvl[1] = 0x03; in pll_calculate()
383 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x03; in pll_calculate()
384 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00; in pll_calculate()
385 cfg->tx_lx_pre_driver_1[0] = 0x00; in pll_calculate()
386 cfg->tx_lx_pre_driver_1[1] = 0x00; in pll_calculate()
387 cfg->tx_lx_pre_driver_1[2] = 0x00; in pll_calculate()
388 cfg->tx_lx_pre_driver_1[3] = 0x00; in pll_calculate()
389 cfg->tx_lx_pre_driver_2[0] = 0x16; in pll_calculate()
390 cfg->tx_lx_pre_driver_2[1] = 0x16; in pll_calculate()
391 cfg->tx_lx_pre_driver_2[2] = 0x16; in pll_calculate()
392 cfg->tx_lx_pre_driver_2[3] = 0x18; in pll_calculate()
393 cfg->tx_lx_res_code_offset[0] = 0x03; in pll_calculate()
394 cfg->tx_lx_res_code_offset[1] = 0x00; in pll_calculate()
395 cfg->tx_lx_res_code_offset[2] = 0x00; in pll_calculate()
396 cfg->tx_lx_res_code_offset[3] = 0x00; in pll_calculate()
398 cfg->tx_lx_tx_drv_lvl[0] = 0x0f; in pll_calculate()
399 cfg->tx_lx_tx_drv_lvl[1] = 0x0f; in pll_calculate()
400 cfg->tx_lx_tx_drv_lvl[2] = 0x0f; in pll_calculate()
401 cfg->tx_lx_tx_drv_lvl[3] = 0x0f; in pll_calculate()
402 cfg->tx_lx_tx_emp_post1_lvl[0] = 0x05; in pll_calculate()
403 cfg->tx_lx_tx_emp_post1_lvl[1] = 0x05; in pll_calculate()
404 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x05; in pll_calculate()
405 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00; in pll_calculate()
406 cfg->tx_lx_pre_driver_1[0] = 0x00; in pll_calculate()
407 cfg->tx_lx_pre_driver_1[1] = 0x00; in pll_calculate()
408 cfg->tx_lx_pre_driver_1[2] = 0x00; in pll_calculate()
409 cfg->tx_lx_pre_driver_1[3] = 0x00; in pll_calculate()
410 cfg->tx_lx_pre_driver_2[0] = 0x0E; in pll_calculate()
411 cfg->tx_lx_pre_driver_2[1] = 0x0E; in pll_calculate()
412 cfg->tx_lx_pre_driver_2[2] = 0x0E; in pll_calculate()
413 cfg->tx_lx_pre_driver_2[3] = 0x0E; in pll_calculate()
414 cfg->tx_lx_res_code_offset[0] = 0x00; in pll_calculate()
415 cfg->tx_lx_res_code_offset[1] = 0x00; in pll_calculate()
416 cfg->tx_lx_res_code_offset[2] = 0x00; in pll_calculate()
417 cfg->tx_lx_res_code_offset[3] = 0x00; in pll_calculate()
419 cfg->tx_lx_tx_drv_lvl[0] = 0x01; in pll_calculate()
420 cfg->tx_lx_tx_drv_lvl[1] = 0x01; in pll_calculate()
421 cfg->tx_lx_tx_drv_lvl[2] = 0x01; in pll_calculate()
422 cfg->tx_lx_tx_drv_lvl[3] = 0x00; in pll_calculate()
423 cfg->tx_lx_tx_emp_post1_lvl[0] = 0x00; in pll_calculate()
424 cfg->tx_lx_tx_emp_post1_lvl[1] = 0x00; in pll_calculate()
425 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x00; in pll_calculate()
426 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00; in pll_calculate()
427 cfg->tx_lx_pre_driver_1[0] = 0x00; in pll_calculate()
428 cfg->tx_lx_pre_driver_1[1] = 0x00; in pll_calculate()
429 cfg->tx_lx_pre_driver_1[2] = 0x00; in pll_calculate()
430 cfg->tx_lx_pre_driver_1[3] = 0x00; in pll_calculate()
431 cfg->tx_lx_pre_driver_2[0] = 0x16; in pll_calculate()
432 cfg->tx_lx_pre_driver_2[1] = 0x16; in pll_calculate()
433 cfg->tx_lx_pre_driver_2[2] = 0x16; in pll_calculate()
434 cfg->tx_lx_pre_driver_2[3] = 0x18; in pll_calculate()
435 cfg->tx_lx_res_code_offset[0] = 0x00; in pll_calculate()
436 cfg->tx_lx_res_code_offset[1] = 0x00; in pll_calculate()
437 cfg->tx_lx_res_code_offset[2] = 0x00; in pll_calculate()
438 cfg->tx_lx_res_code_offset[3] = 0x00; in pll_calculate()
449 struct hdmi_8998_phy_pll_reg_cfg cfg = {}; in hdmi_8998_pll_set_clk_rate() local
452 ret = pll_calculate(rate, parent_rate, &cfg); in hdmi_8998_pll_set_clk_rate()
470 cfg.tx_lx_tx_band[i]); in hdmi_8998_pll_set_clk_rate()
487 cfg.com_svs_mode_clk_sel); in hdmi_8998_pll_set_clk_rate()
494 cfg.com_hsclk_sel); in hdmi_8998_pll_set_clk_rate()
496 cfg.com_lock_cmp_en); in hdmi_8998_pll_set_clk_rate()
499 cfg.com_pll_cctrl_mode0); in hdmi_8998_pll_set_clk_rate()
501 cfg.com_pll_rctrl_mode0); in hdmi_8998_pll_set_clk_rate()
503 cfg.com_cp_ctrl_mode0); in hdmi_8998_pll_set_clk_rate()
505 cfg.com_dec_start_mode0); in hdmi_8998_pll_set_clk_rate()
507 cfg.com_div_frac_start1_mode0); in hdmi_8998_pll_set_clk_rate()
509 cfg.com_div_frac_start2_mode0); in hdmi_8998_pll_set_clk_rate()
511 cfg.com_div_frac_start3_mode0); in hdmi_8998_pll_set_clk_rate()
514 cfg.com_integloop_gain0_mode0); in hdmi_8998_pll_set_clk_rate()
516 cfg.com_integloop_gain1_mode0); in hdmi_8998_pll_set_clk_rate()
519 cfg.com_lock_cmp1_mode0); in hdmi_8998_pll_set_clk_rate()
521 cfg.com_lock_cmp2_mode0); in hdmi_8998_pll_set_clk_rate()
523 cfg.com_lock_cmp3_mode0); in hdmi_8998_pll_set_clk_rate()
527 cfg.com_core_clk_en); in hdmi_8998_pll_set_clk_rate()
529 cfg.com_coreclk_div_mode0); in hdmi_8998_pll_set_clk_rate()
535 cfg.tx_lx_tx_drv_lvl[i]); in hdmi_8998_pll_set_clk_rate()
538 cfg.tx_lx_tx_emp_post1_lvl[i]); in hdmi_8998_pll_set_clk_rate()
541 cfg.tx_lx_pre_driver_1[i]); in hdmi_8998_pll_set_clk_rate()
544 cfg.tx_lx_pre_driver_2[i]); in hdmi_8998_pll_set_clk_rate()
547 cfg.tx_lx_res_code_offset[i]); in hdmi_8998_pll_set_clk_rate()
550 hdmi_phy_write(phy, REG_HDMI_8998_PHY_MODE, cfg.phy_mode); in hdmi_8998_pll_set_clk_rate()