Lines Matching +full:mode +full:- +full:xxx

33 	struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push;  in headc37d_or()
34 const int i = head->base.index; in headc37d_or()
38 /*XXX: This is a dirty hack until OR depth handling is in headc37d_or()
41 switch (asyh->or.depth) { in headc37d_or()
47 depth = asyh->or.depth; in headc37d_or()
56 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) | in headc37d_or()
57 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) | in headc37d_or()
58 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) | in headc37d_or()
67 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc37d_procamp()
68 const int i = head->base.index; in headc37d_procamp()
77 NVVAL(NVC37D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) | in headc37d_procamp()
78 NVVAL(NVC37D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) | in headc37d_procamp()
88 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc37d_dither()
89 const int i = head->base.index; in headc37d_dither()
96 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in headc37d_dither()
97 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in headc37d_dither()
99 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in headc37d_dither()
107 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc37d_curs_clr()
108 const int i = head->base.index; in headc37d_curs_clr()
125 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc37d_curs_set()
126 const int i = head->base.index; in headc37d_curs_set()
134 NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | in headc37d_curs_set()
135 NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in headc37d_curs_set()
146 NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND)); in headc37d_curs_set()
148 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle); in headc37d_curs_set()
149 PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8); in headc37d_curs_set()
157 asyh->curs.format = asyw->image.format; in headc37d_curs_format()
164 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc37d_olut_clr()
165 const int i = head->base.index; in headc37d_olut_clr()
178 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc37d_olut_set()
179 const int i = head->base.index; in headc37d_olut_set()
186 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, SIZE, asyh->olut.size) | in headc37d_olut_set()
187 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, RANGE, asyh->olut.range) | in headc37d_olut_set()
188 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, OUTPUT_MODE, asyh->olut.output_mode), in headc37d_olut_set()
190 HEAD_SET_OFFSET_OUTPUT_LUT(i), asyh->olut.offset >> 8, in headc37d_olut_set()
191 HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), asyh->olut.handle); in headc37d_olut_set()
201 asyh->olut.size = size == 1024 ? NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 : in headc37d_olut()
203 asyh->olut.range = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY; in headc37d_olut()
204 asyh->olut.output_mode = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE; in headc37d_olut()
205 asyh->olut.load = head907d_olut_load; in headc37d_olut()
212 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc37d_mode()
213 struct nv50_head_mode *m = &asyh->mode; in headc37d_mode()
214 const int i = head->base.index; in headc37d_mode()
221 NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) | in headc37d_mode()
222 NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active), in headc37d_mode()
225 NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) | in headc37d_mode()
226 NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce), in headc37d_mode()
229 NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) | in headc37d_mode()
230 NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke), in headc37d_mode()
233 NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) | in headc37d_mode()
234 NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks)); in headc37d_mode()
236 //XXX: in headc37d_mode()
237 PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); in headc37d_mode()
238 PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace); in headc37d_mode()
241 NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000)); in headc37d_mode()
244 NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000)); in headc37d_mode()
246 /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ in headc37d_mode()
257 struct nvif_push *push = &nv50_disp(head->base.base.dev)->core->chan.push; in headc37d_view()
258 const int i = head->base.index; in headc37d_view()
265 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | in headc37d_view()
266 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); in headc37d_view()
269 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | in headc37d_view()
270 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH)); in headc37d_view()
279 for (i = head->base.index * 2, end = i + 2; i < end; i++) in headc37d_static_wndw_map()
280 asyh->wndw.owned |= BIT(i); in headc37d_static_wndw_map()
286 .mode = headc37d_mode,