Lines Matching +defs:val +defs:pixels
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
356 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) in dispc_write_reg()
375 enum mgr_reg_fields regfld, int val) in mgr_fld_write()
932 u32 val; in dispc_ovl_set_pos() local
946 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_input_size() local
958 u32 val; in dispc_ovl_set_output_size() local
1120 u32 val; in dispc_ovl_set_channel_out() local
1182 u32 val; in dispc_ovl_get_channel_out() local
1305 u32 val; in dispc_ovl_set_vid_color_conv() local
1332 u32 val; in dispc_mgr_set_size() local
1602 u32 val; in dispc_ovl_set_fir() local
1625 u32 val; in dispc_ovl_set_vid_accu0() local
1643 u32 val; in dispc_ovl_set_vid_accu1() local
1661 u32 val; in dispc_ovl_set_vid_accu2_0() local
1671 u32 val; in dispc_ovl_set_vid_accu2_1() local
2042 static s32 pixinc(int pixels, u8 ps) in pixinc()
2107 u64 val, blank; in check_horiz_timing_omap3() local
3065 u32 mask, val; in _dispc_mgr_set_lcd_timings() local