27 #define XPP055C272_CMD_ALL_PIXEL_OFF	0x22
28 #define XPP055C272_CMD_ALL_PIXEL_ON	0x23
29 #define XPP055C272_CMD_SETDISP		0xb2
30 #define XPP055C272_CMD_SETRGBIF		0xb3
31 #define XPP055C272_CMD_SETCYC		0xb4
32 #define XPP055C272_CMD_SETBGP		0xb5
33 #define XPP055C272_CMD_SETVCOM		0xb6
34 #define XPP055C272_CMD_SETOTP		0xb7
35 #define XPP055C272_CMD_SETPOWER_EXT	0xb8
36 #define XPP055C272_CMD_SETEXTC		0xb9
37 #define XPP055C272_CMD_SETMIPI		0xbA
38 #define XPP055C272_CMD_SETVDC		0xbc
39 #define XPP055C272_CMD_SETPCR		0xbf
40 #define XPP055C272_CMD_SETSCR		0xc0
41 #define XPP055C272_CMD_SETPOWER		0xc1
42 #define XPP055C272_CMD_SETECO		0xc6
43 #define XPP055C272_CMD_SETPANEL		0xcc
44 #define XPP055C272_CMD_SETGAMMA		0xe0
45 #define XPP055C272_CMD_SETEQ		0xe3
46 #define XPP055C272_CMD_SETGIP1		0xe9
47 #define XPP055C272_CMD_SETGIP2		0xea
71 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83);  in xpp055c272_init_sequence()
73 			       0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00,  in xpp055c272_init_sequence()
74 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25,  in xpp055c272_init_sequence()
75 			       0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01,  in xpp055c272_init_sequence()
76 			       0x00, 0x00, 0x37);  in xpp055c272_init_sequence()
77 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25);  in xpp055c272_init_sequence()
78 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00);  in xpp055c272_init_sequence()
80 			       0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00,  in xpp055c272_init_sequence()
81 			       0x00, 0x00);  in xpp055c272_init_sequence()
83 			       0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,  in xpp055c272_init_sequence()
84 			       0x00);  in xpp055c272_init_sequence()
85 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46);  in xpp055c272_init_sequence()
86 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b);  in xpp055c272_init_sequence()
87 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80);  in xpp055c272_init_sequence()
88 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30);  in xpp055c272_init_sequence()
90 			       0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,  in xpp055c272_init_sequence()
91 			       0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);  in xpp055c272_init_sequence()
93 			       0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd,  in xpp055c272_init_sequence()
94 			       0x67, 0x77, 0x33, 0x33);  in xpp055c272_init_sequence()
95 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff,  in xpp055c272_init_sequence()
96 			       0xff, 0x01, 0xff);  in xpp055c272_init_sequence()
97 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETBGP, 0x09, 0x09);  in xpp055c272_init_sequence()
100 	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVCOM, 0x87, 0x95);  in xpp055c272_init_sequence()
102 			       0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12,  in xpp055c272_init_sequence()
103 			       0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18,  in xpp055c272_init_sequence()
104 			       0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80,  in xpp055c272_init_sequence()
105 			       0x01, 0x00, 0x00, 0x00, 0x48, 0xf8, 0x86, 0x42,  in xpp055c272_init_sequence()
106 			       0x08, 0x88, 0x88, 0x80, 0x88, 0x88, 0x88, 0x58,  in xpp055c272_init_sequence()
107 			       0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88,  in xpp055c272_init_sequence()
108 			       0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,  in xpp055c272_init_sequence()
109 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);  in xpp055c272_init_sequence()
111 			       0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,  in xpp055c272_init_sequence()
112 			       0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35,  in xpp055c272_init_sequence()
113 			       0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f,  in xpp055c272_init_sequence()
114 			       0x88, 0x80, 0x24, 0x68, 0x88, 0x88, 0x84, 0x88,  in xpp055c272_init_sequence()
115 			       0x88, 0x88, 0x23, 0x10, 0x00, 0x00, 0x1c, 0x00,  in xpp055c272_init_sequence()
116 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  in xpp055c272_init_sequence()
117 			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05,  in xpp055c272_init_sequence()
118 			       0xa0, 0x00, 0x00, 0x00, 0x00);  in xpp055c272_init_sequence()
120 			       0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36,  in xpp055c272_init_sequence()
121 			       0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11,  in xpp055c272_init_sequence()
122 			       0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38,  in xpp055c272_init_sequence()
123 			       0x36, 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13,  in xpp055c272_init_sequence()
124 			       0x11, 0x18);  in xpp055c272_init_sequence()
129 	return 0;  in xpp055c272_init_sequence()
139 	if (ret < 0)  in xpp055c272_unprepare()
143 	if (ret < 0) {  in xpp055c272_unprepare()
151 	return 0;  in xpp055c272_unprepare()
162 	if (ret < 0) {  in xpp055c272_prepare()
167 	if (ret < 0) {  in xpp055c272_prepare()
175 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in xpp055c272_prepare()
181 	if (ret < 0) {  in xpp055c272_prepare()
187 	if (ret < 0) {  in xpp055c272_prepare()
196 	if (ret < 0) {  in xpp055c272_prepare()
203 	return 0;  in xpp055c272_prepare()
300 	if (ret < 0) {  in xpp055c272_probe()
306 	return 0;  in xpp055c272_probe()
315 	if (ret < 0)  in xpp055c272_remove()