Lines Matching full:writes

49 	{"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"},
51 	{"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"},
55 	{"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"},
57 	{"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"},
65 	{"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"},
84 	{"CORE", "core-memory-writes", "[CORE] Total memory writes"},
85 	{"L2T", "L2T-memory-writes", "[L2T] Total memory writes"},
86 	{"PTB", "PTB-memory-writes", "[PTB] Total memory writes"},
87 	{"TLB", "TLB-memory-writes", "[TLB] Total memory writes"},
94 	{"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"},
95 	{"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"},
153 	{"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"},
155 	{"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"},
159 	{"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"},
161 	{"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"},
165 	{"CORE", "core-memory-writes", "[CORE] Total memory writes"},
166 	{"L2T", "L2T-memory-writes", "[L2T] Total memory writes"},
167 	{"PTB", "PTB-memory-writes", "[PTB] Total memory writes"},
168 	{"TLB", "TLB-memory-writes", "[TLB] Total memory writes"},
174 	{"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"},
175 	{"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"},
183 	{"AXI", "AXI-max-outstanding-writes", "[AXI] Maximum outstanding write transactions"},