Lines Matching full:mmio
38 static void assert_iir_is_zero(struct xe_mmio *mmio, struct xe_reg reg) in assert_iir_is_zero() argument
40 u32 val = xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
45 drm_WARN(&mmio->tile->xe->drm, 1, in assert_iir_is_zero()
48 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
49 xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
50 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
51 xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
60 struct xe_mmio *mmio = &tile->mmio; in unmask_and_enable() local
66 assert_iir_is_zero(mmio, IIR(irqregs)); in unmask_and_enable()
68 xe_mmio_write32(mmio, IER(irqregs), bits); in unmask_and_enable()
69 xe_mmio_write32(mmio, IMR(irqregs), ~bits); in unmask_and_enable()
72 xe_mmio_read32(mmio, IMR(irqregs)); in unmask_and_enable()
78 struct xe_mmio *mmio = &tile->mmio; in mask_and_disable() local
80 xe_mmio_write32(mmio, IMR(irqregs), ~0); in mask_and_disable()
82 xe_mmio_read32(mmio, IMR(irqregs)); in mask_and_disable()
84 xe_mmio_write32(mmio, IER(irqregs), 0); in mask_and_disable()
87 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
88 xe_mmio_read32(mmio, IIR(irqregs)); in mask_and_disable()
89 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
90 xe_mmio_read32(mmio, IIR(irqregs)); in mask_and_disable()
95 struct xe_mmio *mmio = xe_root_tile_mmio(xe); in xelp_intr_disable() local
97 xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0); in xelp_intr_disable()
105 return xe_mmio_read32(mmio, GFX_MSTR_IRQ); in xelp_intr_disable()
111 struct xe_mmio *mmio = xe_root_tile_mmio(xe); in gu_misc_irq_ack() local
117 iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET)); in gu_misc_irq_ack()
119 xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir); in gu_misc_irq_ack()
126 struct xe_mmio *mmio = xe_root_tile_mmio(xe); in xelp_intr_enable() local
128 xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ); in xelp_intr_enable()
130 xe_mmio_read32(mmio, GFX_MSTR_IRQ); in xelp_intr_enable()
137 struct xe_mmio *mmio = >->mmio; in xe_irq_enable_hwe() local
164 xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask); in xe_irq_enable_hwe()
166 xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask); in xe_irq_enable_hwe()
169 xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask); in xe_irq_enable_hwe()
170 xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask); in xe_irq_enable_hwe()
172 xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
174 xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
176 xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
178 xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
180 xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
182 xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
187 xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask); in xe_irq_enable_hwe()
190 xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
191 xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
192 xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
206 xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, gsc_mask | heci_mask); in xe_irq_enable_hwe()
207 xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~gsc_mask); in xe_irq_enable_hwe()
210 xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~(heci_mask << 16)); in xe_irq_enable_hwe()
216 struct xe_mmio *mmio, in gt_engine_identity() argument
225 xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit)); in gt_engine_identity()
233 ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank)); in gt_engine_identity()
243 xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), ident); in gt_engine_identity()
300 struct xe_mmio *mmio = &tile->mmio; in gt_irq_handler() local
312 intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank)); in gt_irq_handler()
314 identity[bit] = gt_engine_identity(xe, mmio, bank, bit); in gt_irq_handler()
315 xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]); in gt_irq_handler()
381 struct xe_mmio *mmio = xe_root_tile_mmio(xe); in dg1_intr_disable() local
385 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0); in dg1_intr_disable()
388 val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR); in dg1_intr_disable()
392 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val); in dg1_intr_disable()
399 struct xe_mmio *mmio = xe_root_tile_mmio(xe); in dg1_intr_enable() local
401 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); in dg1_intr_enable()
403 xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR); in dg1_intr_enable()
432 struct xe_mmio *mmio = &tile->mmio; in dg1_irq_handler() local
437 master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ); in dg1_irq_handler()
441 * and all MMIO reads will be returned with all 1's. Ignore this in dg1_irq_handler()
450 xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl); in dg1_irq_handler()
475 struct xe_mmio *mmio = &tile->mmio; in gt_irq_reset() local
483 xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0); in gt_irq_reset()
484 xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0); in gt_irq_reset()
486 xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0); in gt_irq_reset()
489 xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~0); in gt_irq_reset()
490 xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~0); in gt_irq_reset()
492 xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0); in gt_irq_reset()
494 xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0); in gt_irq_reset()
496 xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0); in gt_irq_reset()
498 xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0); in gt_irq_reset()
499 xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~0); in gt_irq_reset()
500 xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~0); in gt_irq_reset()
501 xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~0); in gt_irq_reset()
503 xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0); in gt_irq_reset()
505 xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0); in gt_irq_reset()
510 xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0); in gt_irq_reset()
511 xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0); in gt_irq_reset()
512 xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~0); in gt_irq_reset()
515 xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0); in gt_irq_reset()
516 xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK, ~0); in gt_irq_reset()
517 xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE, 0); in gt_irq_reset()
518 xe_mmio_write32(mmio, GUC_SG_INTR_MASK, ~0); in gt_irq_reset()
548 struct xe_mmio *mmio = &tile->mmio; in dg1_irq_reset_mstr() local
550 xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0); in dg1_irq_reset_mstr()