Lines Matching +full:fifo +full:- +full:depth
1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
27 #include <linux/platform_data/i2c-xiic.h>
36 #define DRIVER_NAME "xiic-i2c"
58 * struct xiic_i2c - Internal representation of the XIIC I2C bus
69 * @endianness: big/little-endian byte order
70 * @clk: Pointer to AXI4-lite input clock
114 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
148 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
149 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
151 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
169 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
180 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
181 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
182 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
183 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
184 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
189 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
190 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
194 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
196 /* The following constants specify the depth of the FIFOs */
197 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
198 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
209 * Tx Fifo upper bit masks.
245 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
246 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
255 clk_disable(i2c->clk); in xiic_i2c_runtime_suspend()
265 ret = clk_enable(i2c->clk); in xiic_i2c_runtime_resume()
275 * For the register read and write functions, a little-endian and big-endian
279 * big-endian systems.
284 if (i2c->endianness == LITTLE) in xiic_setreg8()
285 iowrite8(value, i2c->base + reg); in xiic_setreg8()
287 iowrite8(value, i2c->base + reg + 3); in xiic_setreg8()
294 if (i2c->endianness == LITTLE) in xiic_getreg8()
295 ret = ioread8(i2c->base + reg); in xiic_getreg8()
297 ret = ioread8(i2c->base + reg + 3); in xiic_getreg8()
303 if (i2c->endianness == LITTLE) in xiic_setreg16()
304 iowrite16(value, i2c->base + reg); in xiic_setreg16()
306 iowrite16be(value, i2c->base + reg + 2); in xiic_setreg16()
311 if (i2c->endianness == LITTLE) in xiic_setreg32()
312 iowrite32(value, i2c->base + reg); in xiic_setreg32()
314 iowrite32be(value, i2c->base + reg); in xiic_setreg32()
321 if (i2c->endianness == LITTLE) in xiic_getreg32()
322 ret = ioread32(i2c->base + reg); in xiic_getreg32()
324 ret = ioread32be(i2c->base + reg); in xiic_getreg32()
366 dev_err(i2c->dev, "Failed to clear rx fifo\n"); in xiic_clear_rx_fifo()
367 return -ETIMEDOUT; in xiic_clear_rx_fifo()
384 dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); in xiic_wait_tx_empty()
385 return -ETIMEDOUT; in xiic_wait_tx_empty()
393 * xiic_setclk - Sets the configured clock rate
402 * -EINVAL on failure (scl frequency not supported or THIGH is 0)
410 if (!i2c->atomic) in xiic_setclk()
411 dev_dbg(i2c->adap.dev.parent, in xiic_setclk()
412 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n", in xiic_setclk()
413 __func__, i2c->input_clk, i2c->i2c_clk); in xiic_setclk()
416 if (!i2c->i2c_clk || !i2c->input_clk) in xiic_setclk()
419 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000); in xiic_setclk()
421 switch (i2c->i2c_clk) { in xiic_setclk()
432 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n"); in xiic_setclk()
433 return -EINVAL; in xiic_setclk()
443 /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */ in xiic_setclk()
444 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7; in xiic_setclk()
446 return -EINVAL; in xiic_setclk()
448 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1); in xiic_setclk()
450 /* TLOW - Value same as THIGH */ in xiic_setclk()
451 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1); in xiic_setclk()
455 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1); in xiic_setclk()
459 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1); in xiic_setclk()
463 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1); in xiic_setclk()
467 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1); in xiic_setclk()
471 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1); in xiic_setclk()
489 /* Set receive Fifo depth to maximum (zero based). */ in xiic_reinit()
490 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); in xiic_reinit()
492 /* Reset Tx Fifo. */ in xiic_reinit()
495 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ in xiic_reinit()
498 /* make sure RX fifo is empty */ in xiic_reinit()
504 if (!i2c->atomic) in xiic_reinit()
531 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN; in xiic_smbus_block_read_setup()
534 i2c->smbus_block_read = true; in xiic_smbus_block_read_setup()
536 /* Read byte from rx fifo and set message length */ in xiic_smbus_block_read_setup()
539 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len; in xiic_smbus_block_read_setup()
543 /* Set Receive fifo depth */ in xiic_smbus_block_read_setup()
546 * When Rx msg len greater than or equal to Rx fifo capacity in xiic_smbus_block_read_setup()
547 * Receive fifo depth should set to Rx fifo capacity minus 1 in xiic_smbus_block_read_setup()
549 rfd_set = IIC_RX_FIFO_DEPTH - 1; in xiic_smbus_block_read_setup()
550 i2c->rx_msg->len = rxmsg_len + 1; in xiic_smbus_block_read_setup()
559 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN; in xiic_smbus_block_read_setup()
562 * When Rx msg len less than Rx fifo capacity in xiic_smbus_block_read_setup()
563 * Receive fifo depth should set to Rx msg len minus 2 in xiic_smbus_block_read_setup()
565 rfd_set = rxmsg_len - 2; in xiic_smbus_block_read_setup()
566 i2c->rx_msg->len = rxmsg_len + 1; in xiic_smbus_block_read_setup()
574 i2c->tx_msg->len = 3; in xiic_smbus_block_read_setup()
575 i2c->smbus_block_read = false; in xiic_smbus_block_read_setup()
576 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); in xiic_smbus_block_read_setup()
587 if (!i2c->atomic) in xiic_read_rx()
588 dev_dbg(i2c->adap.dev.parent, in xiic_read_rx()
589 "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", in xiic_read_rx()
599 if (!i2c->dynamic) { in xiic_read_rx()
600 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; in xiic_read_rx()
603 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) { in xiic_read_rx()
611 bytes_to_read = bytes_rem - 1; in xiic_read_rx()
622 if (i2c->nmsgs == 1) { in xiic_read_rx()
635 /* Read the fifo */ in xiic_read_rx()
637 i2c->rx_msg->buf[i2c->rx_pos++] = in xiic_read_rx()
641 if (i2c->dynamic) { in xiic_read_rx()
644 /* Receive remaining bytes if less than fifo depth */ in xiic_read_rx()
646 bytes--; in xiic_read_rx()
665 if (i2c->tx_msg || i2c->rx_msg) in xiic_error_check()
666 i2c->atomic_xfer_state = STATE_ERROR; in xiic_error_check()
673 /* return the actual space left in the FIFO */ in xiic_tx_fifo_space()
674 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; in xiic_tx_fifo_space()
684 if (!i2c->atomic) in xiic_fill_tx_fifo()
685 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", in xiic_fill_tx_fifo()
688 while (len--) { in xiic_fill_tx_fifo()
689 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; in xiic_fill_tx_fifo()
691 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { in xiic_fill_tx_fifo()
692 /* last message in transfer -> STOP */ in xiic_fill_tx_fifo()
693 if (i2c->dynamic) { in xiic_fill_tx_fifo()
699 /* Wait till FIFO is empty so STOP is sent last */ in xiic_fill_tx_fifo()
709 if (!i2c->atomic) in xiic_fill_tx_fifo()
710 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); in xiic_fill_tx_fifo()
714 if (i2c->atomic && xiic_error_check(i2c)) in xiic_fill_tx_fifo()
721 i2c->tx_msg = NULL; in xiic_wakeup()
722 i2c->rx_msg = NULL; in xiic_wakeup()
723 i2c->nmsgs = 0; in xiic_wakeup()
724 i2c->state = code; in xiic_wakeup()
725 complete(&i2c->completion); in xiic_wakeup()
743 mutex_lock(&i2c->lock); in xiic_process()
748 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", in xiic_process()
750 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", in xiic_process()
752 i2c->tx_msg, i2c->nmsgs); in xiic_process()
753 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", in xiic_process()
767 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); in xiic_process()
775 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); in xiic_process()
777 if (i2c->rx_msg) { in xiic_process()
781 if (i2c->tx_msg) { in xiic_process()
789 /* Receive register/FIFO is full */ in xiic_process()
792 if (!i2c->rx_msg) { in xiic_process()
793 dev_dbg(i2c->adap.dev.parent, in xiic_process()
802 i2c->rx_msg = NULL; in xiic_process()
807 dev_dbg(i2c->adap.dev.parent, in xiic_process()
809 __func__, i2c->nmsgs); in xiic_process()
815 if (i2c->nmsgs > 1) { in xiic_process()
816 i2c->nmsgs--; in xiic_process()
817 i2c->tx_msg++; in xiic_process()
818 dev_dbg(i2c->adap.dev.parent, in xiic_process()
825 /* Transmit register/FIFO is empty or ½ empty */ in xiic_process()
830 if (!i2c->tx_msg) { in xiic_process()
831 dev_dbg(i2c->adap.dev.parent, in xiic_process()
840 dev_dbg(i2c->adap.dev.parent, in xiic_process()
842 __func__, i2c->nmsgs); in xiic_process()
843 /* Don't move onto the next message until the TX FIFO empties, in xiic_process()
846 if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) { in xiic_process()
847 i2c->nmsgs--; in xiic_process()
848 i2c->tx_msg++; in xiic_process()
853 dev_dbg(i2c->adap.dev.parent, in xiic_process()
867 if (i2c->tx_msg && i2c->smbus_block_read) { in xiic_process()
868 i2c->smbus_block_read = false; in xiic_process()
870 i2c->tx_msg->len = 1; in xiic_process()
873 if (!i2c->tx_msg) in xiic_process()
878 if (i2c->nmsgs == 1 && !i2c->rx_msg && in xiic_process()
886 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
896 mutex_unlock(&i2c->lock); in xiic_process()
904 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; in xiic_bus_busy()
917 while (err && tries--) { in xiic_wait_not_busy()
918 if (i2c->atomic) in xiic_wait_not_busy()
942 i2c->rx_msg = NULL; in xiic_recv_atomic()
946 if (i2c->nmsgs > 1) { in xiic_recv_atomic()
947 i2c->nmsgs--; in xiic_recv_atomic()
948 i2c->tx_msg++; in xiic_recv_atomic()
957 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; in xiic_start_recv()
959 if (!i2c->atomic) in xiic_start_recv()
960 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_recv()
967 if (i2c->dynamic) { in xiic_start_recv()
983 rx_watermark = msg->len; in xiic_start_recv()
987 bytes--; in xiic_start_recv()
996 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; in xiic_start_recv()
997 val |= msg->len; in xiic_start_recv()
1004 * If previous message is Tx, make sure that Tx FIFO is empty in xiic_start_recv()
1007 * still bytes to be transmitted in FIFO in xiic_start_recv()
1009 if (i2c->prev_msg_tx) { in xiic_start_recv()
1019 /* Set Receive fifo depth */ in xiic_start_recv()
1020 rx_watermark = msg->len; in xiic_start_recv()
1022 rfd_set = IIC_RX_FIFO_DEPTH - 1; in xiic_start_recv()
1024 rfd_set = rx_watermark - 1; in xiic_start_recv()
1027 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) { in xiic_start_recv()
1034 rfd_set = rx_watermark - 2; in xiic_start_recv()
1060 if (!i2c->atomic) in xiic_start_recv()
1061 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", in xiic_start_recv()
1066 if (i2c->nmsgs == 1) in xiic_start_recv()
1071 i2c->tx_pos = msg->len; in xiic_start_recv()
1073 i2c->prev_msg_tx = false; in xiic_start_recv()
1076 if (!i2c->atomic) in xiic_start_recv()
1088 data = i2c->tx_msg->buf[i2c->tx_pos]; in xiic_send_rem_atomic()
1089 i2c->tx_pos++; in xiic_send_rem_atomic()
1090 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { in xiic_send_rem_atomic()
1091 /* last message in transfer -> STOP */ in xiic_send_rem_atomic()
1092 if (i2c->dynamic) { in xiic_send_rem_atomic()
1098 /* Wait till FIFO is empty so STOP is sent last */ in xiic_send_rem_atomic()
1115 if (i2c->nmsgs > 1) { in xiic_send_rem_atomic()
1116 i2c->nmsgs--; in xiic_send_rem_atomic()
1117 i2c->tx_msg++; in xiic_send_rem_atomic()
1128 struct i2c_msg *msg = i2c->tx_msg; in xiic_start_send()
1130 if (!i2c->atomic) { in xiic_start_send()
1131 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", in xiic_start_send()
1132 __func__, msg, msg->len); in xiic_start_send()
1133 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_send()
1138 if (i2c->dynamic) { in xiic_start_send()
1143 if (i2c->nmsgs == 1 && msg->len == 0) in xiic_start_send()
1144 /* no data and last message -> add STOP */ in xiic_start_send()
1153 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? in xiic_start_send()
1159 * If previous message is Tx, make sure that Tx FIFO is empty in xiic_start_send()
1162 * still bytes to be transmitted in FIFO in xiic_start_send()
1164 if (i2c->prev_msg_tx) { in xiic_start_send()
1181 /* Write address to FIFO */ in xiic_start_send()
1185 /* Fill fifo */ in xiic_start_send()
1202 i2c->prev_msg_tx = true; in xiic_start_send()
1204 if (i2c->atomic && !i2c->atomic_xfer_state) in xiic_start_send()
1212 if (!i2c->atomic) in __xiic_start_xfer()
1213 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", in __xiic_start_xfer()
1214 __func__, i2c->tx_msg, fifo_space); in __xiic_start_xfer()
1216 if (!i2c->tx_msg) in __xiic_start_xfer()
1219 if (i2c->atomic && xiic_error_check(i2c)) in __xiic_start_xfer()
1222 i2c->rx_pos = 0; in __xiic_start_xfer()
1223 i2c->tx_pos = 0; in __xiic_start_xfer()
1224 i2c->state = STATE_START; in __xiic_start_xfer()
1225 if (i2c->tx_msg->flags & I2C_M_RD) { in __xiic_start_xfer()
1226 /* we dont date putting several reads in the FIFO */ in __xiic_start_xfer()
1238 if (i2c->atomic) in xiic_start_xfer()
1239 spin_lock(&i2c->atomic_lock); in xiic_start_xfer()
1241 mutex_lock(&i2c->lock); in xiic_start_xfer()
1243 if (i2c->tx_msg || i2c->rx_msg) { in xiic_start_xfer()
1244 dev_err(i2c->adap.dev.parent, in xiic_start_xfer()
1246 ret = -EBUSY; in xiic_start_xfer()
1250 i2c->atomic_xfer_state = STATE_DONE; in xiic_start_xfer()
1257 if (!i2c->singlemaster) { in xiic_start_xfer()
1262 * then try to recover by re-initializing the controller and check in xiic_start_xfer()
1265 dev_warn(i2c->adap.dev.parent, "I2C bus busy timeout, reinitializing\n"); in xiic_start_xfer()
1275 i2c->tx_msg = msgs; in xiic_start_xfer()
1276 i2c->rx_msg = NULL; in xiic_start_xfer()
1277 i2c->nmsgs = num; in xiic_start_xfer()
1279 if (!i2c->atomic) in xiic_start_xfer()
1280 init_completion(&i2c->completion); in xiic_start_xfer()
1283 i2c->dynamic = true; in xiic_start_xfer()
1286 i2c->prev_msg_tx = false; in xiic_start_xfer()
1293 * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions. in xiic_start_xfer()
1297 for (count = 0; count < i2c->nmsgs; count++) { in xiic_start_xfer()
1298 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && in xiic_start_xfer()
1299 (i2c->tx_msg[count].flags & I2C_M_RD); in xiic_start_xfer()
1300 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && in xiic_start_xfer()
1301 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); in xiic_start_xfer()
1302 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); in xiic_start_xfer()
1305 i2c->dynamic = false; in xiic_start_xfer()
1315 if (i2c->atomic) in xiic_start_xfer()
1316 spin_unlock(&i2c->atomic_lock); in xiic_start_xfer()
1318 mutex_unlock(&i2c->lock); in xiic_start_xfer()
1328 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, in xiic_xfer()
1331 err = pm_runtime_resume_and_get(i2c->dev); in xiic_xfer()
1339 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); in xiic_xfer()
1340 mutex_lock(&i2c->lock); in xiic_xfer()
1342 i2c->tx_msg = NULL; in xiic_xfer()
1343 i2c->rx_msg = NULL; in xiic_xfer()
1344 i2c->nmsgs = 0; in xiic_xfer()
1345 err = -ETIMEDOUT; in xiic_xfer()
1347 err = (i2c->state == STATE_DONE) ? num : -EIO; in xiic_xfer()
1349 mutex_unlock(&i2c->lock); in xiic_xfer()
1352 pm_runtime_mark_last_busy(i2c->dev); in xiic_xfer()
1353 pm_runtime_put_autosuspend(i2c->dev); in xiic_xfer()
1363 err = xiic_i2c_runtime_resume(i2c->dev); in xiic_xfer_atomic()
1367 i2c->atomic = true; in xiic_xfer_atomic()
1372 err = readl_poll_timeout_atomic(i2c->base + XIIC_SR_REG_OFFSET, in xiic_xfer_atomic()
1377 err = -ETIMEDOUT; in xiic_xfer_atomic()
1379 spin_lock(&i2c->atomic_lock); in xiic_xfer_atomic()
1380 if (err || i2c->state) { in xiic_xfer_atomic()
1381 i2c->tx_msg = NULL; in xiic_xfer_atomic()
1382 i2c->rx_msg = NULL; in xiic_xfer_atomic()
1383 i2c->nmsgs = 0; in xiic_xfer_atomic()
1386 err = (i2c->atomic_xfer_state == STATE_DONE) ? num : -EIO; in xiic_xfer_atomic()
1387 spin_unlock(&i2c->atomic_lock); in xiic_xfer_atomic()
1389 i2c->atomic = false; in xiic_xfer_atomic()
1390 xiic_i2c_runtime_suspend(i2c->dev); in xiic_xfer_atomic()
1418 { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 },
1419 { .compatible = "xlnx,axi-iic-2.1", },
1435 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in xiic_i2c_probe()
1437 return -ENOMEM; in xiic_i2c_probe()
1439 match = of_match_node(xiic_of_match, pdev->dev.of_node); in xiic_i2c_probe()
1440 if (match && match->data) { in xiic_i2c_probe()
1441 const struct xiic_version_data *data = match->data; in xiic_i2c_probe()
1443 i2c->quirks = data->quirks; in xiic_i2c_probe()
1446 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in xiic_i2c_probe()
1447 if (IS_ERR(i2c->base)) in xiic_i2c_probe()
1448 return PTR_ERR(i2c->base); in xiic_i2c_probe()
1454 pdata = dev_get_platdata(&pdev->dev); in xiic_i2c_probe()
1458 i2c->adap = xiic_adapter; in xiic_i2c_probe()
1459 i2c_set_adapdata(&i2c->adap, i2c); in xiic_i2c_probe()
1460 i2c->adap.dev.parent = &pdev->dev; in xiic_i2c_probe()
1461 i2c->adap.dev.of_node = pdev->dev.of_node; in xiic_i2c_probe()
1462 snprintf(i2c->adap.name, sizeof(i2c->adap.name), in xiic_i2c_probe()
1463 DRIVER_NAME " %s", pdev->name); in xiic_i2c_probe()
1465 mutex_init(&i2c->lock); in xiic_i2c_probe()
1466 spin_lock_init(&i2c->atomic_lock); in xiic_i2c_probe()
1468 i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL); in xiic_i2c_probe()
1469 if (IS_ERR(i2c->clk)) in xiic_i2c_probe()
1470 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), in xiic_i2c_probe()
1473 i2c->dev = &pdev->dev; in xiic_i2c_probe()
1474 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); in xiic_i2c_probe()
1475 pm_runtime_use_autosuspend(i2c->dev); in xiic_i2c_probe()
1476 pm_runtime_set_active(i2c->dev); in xiic_i2c_probe()
1477 pm_runtime_enable(i2c->dev); in xiic_i2c_probe()
1480 i2c->input_clk = clk_get_rate(i2c->clk); in xiic_i2c_probe()
1481 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", in xiic_i2c_probe()
1482 &i2c->i2c_clk); in xiic_i2c_probe()
1483 /* If clock-frequency not specified in DT, do not configure in SW */ in xiic_i2c_probe()
1484 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ) in xiic_i2c_probe()
1485 i2c->i2c_clk = 0; in xiic_i2c_probe()
1487 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in xiic_i2c_probe()
1489 pdev->name, i2c); in xiic_i2c_probe()
1492 dev_err(&pdev->dev, "Cannot claim IRQ\n"); in xiic_i2c_probe()
1496 i2c->singlemaster = in xiic_i2c_probe()
1497 of_property_read_bool(pdev->dev.of_node, "single-master"); in xiic_i2c_probe()
1501 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not in xiic_i2c_probe()
1504 i2c->endianness = LITTLE; in xiic_i2c_probe()
1509 i2c->endianness = BIG; in xiic_i2c_probe()
1513 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); in xiic_i2c_probe()
1518 ret = i2c_add_adapter(&i2c->adap); in xiic_i2c_probe()
1526 for (i = 0; i < pdata->num_devices; i++) in xiic_i2c_probe()
1527 i2c_new_client_device(&i2c->adap, pdata->devices + i); in xiic_i2c_probe()
1530 dev_dbg(&pdev->dev, "mmio %08lx irq %d scl clock frequency %d\n", in xiic_i2c_probe()
1531 (unsigned long)res->start, irq, i2c->i2c_clk); in xiic_i2c_probe()
1536 pm_runtime_disable(&pdev->dev); in xiic_i2c_probe()
1537 pm_runtime_set_suspended(&pdev->dev); in xiic_i2c_probe()
1548 i2c_del_adapter(&i2c->adap); in xiic_i2c_remove()
1550 ret = pm_runtime_get_sync(i2c->dev); in xiic_i2c_remove()
1553 dev_warn(&pdev->dev, "Failed to activate device for removal (%pe)\n", in xiic_i2c_remove()
1558 pm_runtime_put_sync(i2c->dev); in xiic_i2c_remove()
1559 pm_runtime_disable(&pdev->dev); in xiic_i2c_remove()
1560 pm_runtime_set_suspended(&pdev->dev); in xiic_i2c_remove()
1561 pm_runtime_dont_use_autosuspend(&pdev->dev); in xiic_i2c_remove()
1582 MODULE_AUTHOR("info@mocean-labs.com");