Lines Matching full:i2c
3 * i2c-xiic.c
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
36 #define DRIVER_NAME "xiic-i2c"
58 * struct xiic_i2c - Internal representation of the XIIC I2C bus
77 * @input_clk: Input clock to I2C controller
78 * @i2c_clk: I2C SCL frequency
114 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
129 /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
156 * setting i2c clock frequency for the line.
245 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) argument
246 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) argument
248 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
249 static void __xiic_start_xfer(struct xiic_i2c *i2c);
253 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_suspend() local
255 clk_disable(i2c->clk); in xiic_i2c_runtime_suspend()
262 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_resume() local
265 ret = clk_enable(i2c->clk); in xiic_i2c_runtime_resume()
282 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) in xiic_setreg8() argument
284 if (i2c->endianness == LITTLE) in xiic_setreg8()
285 iowrite8(value, i2c->base + reg); in xiic_setreg8()
287 iowrite8(value, i2c->base + reg + 3); in xiic_setreg8()
290 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) in xiic_getreg8() argument
294 if (i2c->endianness == LITTLE) in xiic_getreg8()
295 ret = ioread8(i2c->base + reg); in xiic_getreg8()
297 ret = ioread8(i2c->base + reg + 3); in xiic_getreg8()
301 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) in xiic_setreg16() argument
303 if (i2c->endianness == LITTLE) in xiic_setreg16()
304 iowrite16(value, i2c->base + reg); in xiic_setreg16()
306 iowrite16be(value, i2c->base + reg + 2); in xiic_setreg16()
309 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) in xiic_setreg32() argument
311 if (i2c->endianness == LITTLE) in xiic_setreg32()
312 iowrite32(value, i2c->base + reg); in xiic_setreg32()
314 iowrite32be(value, i2c->base + reg); in xiic_setreg32()
317 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) in xiic_getreg32() argument
321 if (i2c->endianness == LITTLE) in xiic_getreg32()
322 ret = ioread32(i2c->base + reg); in xiic_getreg32()
324 ret = ioread32be(i2c->base + reg); in xiic_getreg32()
328 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) in xiic_irq_dis() argument
330 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_dis()
332 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); in xiic_irq_dis()
335 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_en() argument
337 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_en()
339 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); in xiic_irq_en()
342 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr() argument
344 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_irq_clr()
346 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); in xiic_irq_clr()
349 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr_en() argument
351 xiic_irq_clr(i2c, mask); in xiic_irq_clr_en()
352 xiic_irq_en(i2c, mask); in xiic_irq_clr_en()
355 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) in xiic_clear_rx_fifo() argument
361 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_clear_rx_fifo()
363 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { in xiic_clear_rx_fifo()
364 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_clear_rx_fifo()
366 dev_err(i2c->dev, "Failed to clear rx fifo\n"); in xiic_clear_rx_fifo()
374 static int xiic_wait_tx_empty(struct xiic_i2c *i2c) in xiic_wait_tx_empty() argument
380 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_wait_tx_empty()
382 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { in xiic_wait_tx_empty()
384 dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); in xiic_wait_tx_empty()
394 * @i2c: Pointer to the xiic device structure
398 * AXI I2C PG and NXP I2C Spec.
404 static int xiic_setclk(struct xiic_i2c *i2c) in xiic_setclk() argument
410 if (!i2c->atomic) in xiic_setclk()
411 dev_dbg(i2c->adap.dev.parent, in xiic_setclk()
412 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n", in xiic_setclk()
413 __func__, i2c->input_clk, i2c->i2c_clk); in xiic_setclk()
416 if (!i2c->i2c_clk || !i2c->input_clk) in xiic_setclk()
419 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000); in xiic_setclk()
421 switch (i2c->i2c_clk) { in xiic_setclk()
432 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n"); in xiic_setclk()
439 * period to get the number of clock cycles required. Refer Xilinx AXI I2C in xiic_setclk()
440 * PG document and I2C specification for further details. in xiic_setclk()
444 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7; in xiic_setclk()
448 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1); in xiic_setclk()
451 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1); in xiic_setclk()
455 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1); in xiic_setclk()
459 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1); in xiic_setclk()
463 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1); in xiic_setclk()
467 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1); in xiic_setclk()
471 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1); in xiic_setclk()
474 xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1); in xiic_setclk()
479 static int xiic_reinit(struct xiic_i2c *i2c) in xiic_reinit() argument
483 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_reinit()
485 ret = xiic_setclk(i2c); in xiic_reinit()
490 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); in xiic_reinit()
493 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_reinit()
496 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); in xiic_reinit()
499 ret = xiic_clear_rx_fifo(i2c); in xiic_reinit()
504 if (!i2c->atomic) in xiic_reinit()
505 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); in xiic_reinit()
507 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); in xiic_reinit()
512 static void xiic_deinit(struct xiic_i2c *i2c) in xiic_deinit() argument
516 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_deinit()
519 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_deinit()
520 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); in xiic_deinit()
523 static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) in xiic_smbus_block_read_setup() argument
531 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN; in xiic_smbus_block_read_setup()
534 i2c->smbus_block_read = true; in xiic_smbus_block_read_setup()
537 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_smbus_block_read_setup()
539 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len; in xiic_smbus_block_read_setup()
550 i2c->rx_msg->len = rxmsg_len + 1; in xiic_smbus_block_read_setup()
559 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN; in xiic_smbus_block_read_setup()
566 i2c->rx_msg->len = rxmsg_len + 1; in xiic_smbus_block_read_setup()
568 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); in xiic_smbus_block_read_setup()
574 i2c->tx_msg->len = 3; in xiic_smbus_block_read_setup()
575 i2c->smbus_block_read = false; in xiic_smbus_block_read_setup()
576 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); in xiic_smbus_block_read_setup()
579 static void xiic_read_rx(struct xiic_i2c *i2c) in xiic_read_rx() argument
585 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; in xiic_read_rx()
587 if (!i2c->atomic) in xiic_read_rx()
588 dev_dbg(i2c->adap.dev.parent, in xiic_read_rx()
590 __func__, bytes_in_fifo, xiic_rx_space(i2c), in xiic_read_rx()
591 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_read_rx()
592 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_read_rx()
594 if (bytes_in_fifo > xiic_rx_space(i2c)) in xiic_read_rx()
595 bytes_in_fifo = xiic_rx_space(i2c); in xiic_read_rx()
599 if (!i2c->dynamic) { in xiic_read_rx()
600 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo; in xiic_read_rx()
603 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) { in xiic_read_rx()
604 xiic_smbus_block_read_setup(i2c); in xiic_read_rx()
615 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_read_rx()
616 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | in xiic_read_rx()
622 if (i2c->nmsgs == 1) { in xiic_read_rx()
623 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_read_rx()
624 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & in xiic_read_rx()
629 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_read_rx()
630 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & in xiic_read_rx()
637 i2c->rx_msg->buf[i2c->rx_pos++] = in xiic_read_rx()
638 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_read_rx()
641 if (i2c->dynamic) { in xiic_read_rx()
645 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH); in xiic_read_rx()
647 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); in xiic_read_rx()
651 static bool xiic_error_check(struct xiic_i2c *i2c) in xiic_error_check() argument
656 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_error_check()
657 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_error_check()
663 xiic_reinit(i2c); in xiic_error_check()
665 if (i2c->tx_msg || i2c->rx_msg) in xiic_error_check()
666 i2c->atomic_xfer_state = STATE_ERROR; in xiic_error_check()
671 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) in xiic_tx_fifo_space() argument
674 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; in xiic_tx_fifo_space()
677 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) in xiic_fill_tx_fifo() argument
679 u8 fifo_space = xiic_tx_fifo_space(i2c); in xiic_fill_tx_fifo()
680 int len = xiic_tx_space(i2c); in xiic_fill_tx_fifo()
684 if (!i2c->atomic) in xiic_fill_tx_fifo()
685 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", in xiic_fill_tx_fifo()
689 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; in xiic_fill_tx_fifo()
691 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { in xiic_fill_tx_fifo()
693 if (i2c->dynamic) { in xiic_fill_tx_fifo()
700 status = xiic_wait_tx_empty(i2c); in xiic_fill_tx_fifo()
705 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_fill_tx_fifo()
706 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & in xiic_fill_tx_fifo()
709 if (!i2c->atomic) in xiic_fill_tx_fifo()
710 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); in xiic_fill_tx_fifo()
712 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_fill_tx_fifo()
714 if (i2c->atomic && xiic_error_check(i2c)) in xiic_fill_tx_fifo()
719 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code) in xiic_wakeup() argument
721 i2c->tx_msg = NULL; in xiic_wakeup()
722 i2c->rx_msg = NULL; in xiic_wakeup()
723 i2c->nmsgs = 0; in xiic_wakeup()
724 i2c->state = code; in xiic_wakeup()
725 complete(&i2c->completion); in xiic_wakeup()
730 struct xiic_i2c *i2c = dev_id; in xiic_process() local
743 mutex_lock(&i2c->lock); in xiic_process()
744 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_process()
745 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_process()
748 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", in xiic_process()
750 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", in xiic_process()
751 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_process()
752 i2c->tx_msg, i2c->nmsgs); in xiic_process()
753 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n", in xiic_process()
754 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_process()
755 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_process()
767 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); in xiic_process()
773 ret = xiic_reinit(i2c); in xiic_process()
775 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); in xiic_process()
777 if (i2c->rx_msg) { in xiic_process()
781 if (i2c->tx_msg) { in xiic_process()
792 if (!i2c->rx_msg) { in xiic_process()
793 dev_dbg(i2c->adap.dev.parent, in xiic_process()
795 xiic_clear_rx_fifo(i2c); in xiic_process()
799 xiic_read_rx(i2c); in xiic_process()
800 if (xiic_rx_space(i2c) == 0) { in xiic_process()
802 i2c->rx_msg = NULL; in xiic_process()
807 dev_dbg(i2c->adap.dev.parent, in xiic_process()
809 __func__, i2c->nmsgs); in xiic_process()
815 if (i2c->nmsgs > 1) { in xiic_process()
816 i2c->nmsgs--; in xiic_process()
817 i2c->tx_msg++; in xiic_process()
818 dev_dbg(i2c->adap.dev.parent, in xiic_process()
830 if (!i2c->tx_msg) { in xiic_process()
831 dev_dbg(i2c->adap.dev.parent, in xiic_process()
836 if (xiic_tx_space(i2c)) { in xiic_process()
837 xiic_fill_tx_fifo(i2c); in xiic_process()
840 dev_dbg(i2c->adap.dev.parent, in xiic_process()
842 __func__, i2c->nmsgs); in xiic_process()
846 if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) { in xiic_process()
847 i2c->nmsgs--; in xiic_process()
848 i2c->tx_msg++; in xiic_process()
851 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_process()
853 dev_dbg(i2c->adap.dev.parent, in xiic_process()
865 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); in xiic_process()
867 if (i2c->tx_msg && i2c->smbus_block_read) { in xiic_process()
868 i2c->smbus_block_read = false; in xiic_process()
870 i2c->tx_msg->len = 1; in xiic_process()
873 if (!i2c->tx_msg) in xiic_process()
878 if (i2c->nmsgs == 1 && !i2c->rx_msg && in xiic_process()
879 xiic_tx_space(i2c) == 0) in xiic_process()
886 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
888 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); in xiic_process()
890 __xiic_start_xfer(i2c); in xiic_process()
892 xiic_wakeup(i2c, wakeup_code); in xiic_process()
896 mutex_unlock(&i2c->lock); in xiic_process()
900 static int xiic_bus_busy(struct xiic_i2c *i2c) in xiic_bus_busy() argument
902 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_bus_busy()
907 static int xiic_wait_not_busy(struct xiic_i2c *i2c) in xiic_wait_not_busy() argument
916 err = xiic_bus_busy(i2c); in xiic_wait_not_busy()
918 if (i2c->atomic) in xiic_wait_not_busy()
922 err = xiic_bus_busy(i2c); in xiic_wait_not_busy()
928 static void xiic_recv_atomic(struct xiic_i2c *i2c) in xiic_recv_atomic() argument
930 while (xiic_rx_space(i2c)) { in xiic_recv_atomic()
931 if (xiic_getreg32(i2c, XIIC_IISR_OFFSET) & XIIC_INTR_RX_FULL_MASK) { in xiic_recv_atomic()
932 xiic_read_rx(i2c); in xiic_recv_atomic()
935 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | in xiic_recv_atomic()
938 if (xiic_error_check(i2c)) in xiic_recv_atomic()
942 i2c->rx_msg = NULL; in xiic_recv_atomic()
943 xiic_irq_clr_en(i2c, XIIC_INTR_TX_ERROR_MASK); in xiic_recv_atomic()
946 if (i2c->nmsgs > 1) { in xiic_recv_atomic()
947 i2c->nmsgs--; in xiic_recv_atomic()
948 i2c->tx_msg++; in xiic_recv_atomic()
949 __xiic_start_xfer(i2c); in xiic_recv_atomic()
953 static void xiic_start_recv(struct xiic_i2c *i2c) in xiic_start_recv() argument
957 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; in xiic_start_recv()
959 if (!i2c->atomic) in xiic_start_recv()
960 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_recv()
961 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_recv()
962 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_recv()
965 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); in xiic_start_recv()
967 if (i2c->dynamic) { in xiic_start_recv()
972 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | in xiic_start_recv()
988 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes); in xiic_start_recv()
991 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
996 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0; in xiic_start_recv()
999 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); in xiic_start_recv()
1001 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
1009 if (i2c->prev_msg_tx) { in xiic_start_recv()
1012 status = xiic_wait_tx_empty(i2c); in xiic_start_recv()
1017 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_start_recv()
1027 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) { in xiic_start_recv()
1039 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | in xiic_start_recv()
1044 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); in xiic_start_recv()
1047 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | in xiic_start_recv()
1051 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
1056 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | in xiic_start_recv()
1060 if (!i2c->atomic) in xiic_start_recv()
1061 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", in xiic_start_recv()
1062 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_recv()
1063 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_recv()
1066 if (i2c->nmsgs == 1) in xiic_start_recv()
1068 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
1071 i2c->tx_pos = msg->len; in xiic_start_recv()
1073 i2c->prev_msg_tx = false; in xiic_start_recv()
1076 if (!i2c->atomic) in xiic_start_recv()
1077 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); in xiic_start_recv()
1079 xiic_recv_atomic(i2c); in xiic_start_recv()
1082 static void xiic_send_rem_atomic(struct xiic_i2c *i2c) in xiic_send_rem_atomic() argument
1084 while (xiic_tx_space(i2c)) { in xiic_send_rem_atomic()
1085 if (xiic_tx_fifo_space(i2c)) { in xiic_send_rem_atomic()
1088 data = i2c->tx_msg->buf[i2c->tx_pos]; in xiic_send_rem_atomic()
1089 i2c->tx_pos++; in xiic_send_rem_atomic()
1090 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { in xiic_send_rem_atomic()
1092 if (i2c->dynamic) { in xiic_send_rem_atomic()
1099 status = xiic_wait_tx_empty(i2c); in xiic_send_rem_atomic()
1104 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_send_rem_atomic()
1105 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & in xiic_send_rem_atomic()
1109 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_send_rem_atomic()
1111 if (xiic_error_check(i2c)) in xiic_send_rem_atomic()
1115 if (i2c->nmsgs > 1) { in xiic_send_rem_atomic()
1116 i2c->nmsgs--; in xiic_send_rem_atomic()
1117 i2c->tx_msg++; in xiic_send_rem_atomic()
1118 __xiic_start_xfer(i2c); in xiic_send_rem_atomic()
1120 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_send_rem_atomic()
1124 static void xiic_start_send(struct xiic_i2c *i2c) in xiic_start_send() argument
1128 struct i2c_msg *msg = i2c->tx_msg; in xiic_start_send()
1130 if (!i2c->atomic) { in xiic_start_send()
1131 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", in xiic_start_send()
1133 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_send()
1134 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_send()
1135 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_send()
1138 if (i2c->dynamic) { in xiic_start_send()
1143 if (i2c->nmsgs == 1 && msg->len == 0) in xiic_start_send()
1147 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_start_send()
1150 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | in xiic_start_send()
1153 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? in xiic_start_send()
1156 xiic_fill_tx_fifo(i2c); in xiic_start_send()
1164 if (i2c->prev_msg_tx) { in xiic_start_send()
1167 status = xiic_wait_tx_empty(i2c); in xiic_start_send()
1172 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_start_send()
1175 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr | in xiic_start_send()
1183 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_start_send()
1186 xiic_fill_tx_fifo(i2c); in xiic_start_send()
1190 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_start_send()
1191 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | in xiic_start_send()
1197 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | in xiic_start_send()
1202 i2c->prev_msg_tx = true; in xiic_start_send()
1204 if (i2c->atomic && !i2c->atomic_xfer_state) in xiic_start_send()
1205 xiic_send_rem_atomic(i2c); in xiic_start_send()
1208 static void __xiic_start_xfer(struct xiic_i2c *i2c) in __xiic_start_xfer() argument
1210 int fifo_space = xiic_tx_fifo_space(i2c); in __xiic_start_xfer()
1212 if (!i2c->atomic) in __xiic_start_xfer()
1213 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", in __xiic_start_xfer()
1214 __func__, i2c->tx_msg, fifo_space); in __xiic_start_xfer()
1216 if (!i2c->tx_msg) in __xiic_start_xfer()
1219 if (i2c->atomic && xiic_error_check(i2c)) in __xiic_start_xfer()
1222 i2c->rx_pos = 0; in __xiic_start_xfer()
1223 i2c->tx_pos = 0; in __xiic_start_xfer()
1224 i2c->state = STATE_START; in __xiic_start_xfer()
1225 if (i2c->tx_msg->flags & I2C_M_RD) { in __xiic_start_xfer()
1227 xiic_start_recv(i2c); in __xiic_start_xfer()
1229 xiic_start_send(i2c); in __xiic_start_xfer()
1233 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) in xiic_start_xfer() argument
1238 if (i2c->atomic) in xiic_start_xfer()
1239 spin_lock(&i2c->atomic_lock); in xiic_start_xfer()
1241 mutex_lock(&i2c->lock); in xiic_start_xfer()
1243 if (i2c->tx_msg || i2c->rx_msg) { in xiic_start_xfer()
1244 dev_err(i2c->adap.dev.parent, in xiic_start_xfer()
1250 i2c->atomic_xfer_state = STATE_DONE; in xiic_start_xfer()
1254 * should ignore it, since bus will never be released and i2c will be in xiic_start_xfer()
1257 if (!i2c->singlemaster) { in xiic_start_xfer()
1258 ret = xiic_wait_not_busy(i2c); in xiic_start_xfer()
1265 dev_warn(i2c->adap.dev.parent, "I2C bus busy timeout, reinitializing\n"); in xiic_start_xfer()
1266 ret = xiic_reinit(i2c); in xiic_start_xfer()
1269 ret = xiic_wait_not_busy(i2c); in xiic_start_xfer()
1275 i2c->tx_msg = msgs; in xiic_start_xfer()
1276 i2c->rx_msg = NULL; in xiic_start_xfer()
1277 i2c->nmsgs = num; in xiic_start_xfer()
1279 if (!i2c->atomic) in xiic_start_xfer()
1280 init_completion(&i2c->completion); in xiic_start_xfer()
1283 i2c->dynamic = true; in xiic_start_xfer()
1286 i2c->prev_msg_tx = false; in xiic_start_xfer()
1297 for (count = 0; count < i2c->nmsgs; count++) { in xiic_start_xfer()
1298 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) && in xiic_start_xfer()
1299 (i2c->tx_msg[count].flags & I2C_M_RD); in xiic_start_xfer()
1300 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) && in xiic_start_xfer()
1301 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC); in xiic_start_xfer()
1302 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN); in xiic_start_xfer()
1305 i2c->dynamic = false; in xiic_start_xfer()
1310 ret = xiic_reinit(i2c); in xiic_start_xfer()
1312 __xiic_start_xfer(i2c); in xiic_start_xfer()
1315 if (i2c->atomic) in xiic_start_xfer()
1316 spin_unlock(&i2c->atomic_lock); in xiic_start_xfer()
1318 mutex_unlock(&i2c->lock); in xiic_start_xfer()
1325 struct xiic_i2c *i2c = i2c_get_adapdata(adap); in xiic_xfer() local
1329 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); in xiic_xfer()
1331 err = pm_runtime_resume_and_get(i2c->dev); in xiic_xfer()
1335 err = xiic_start_xfer(i2c, msgs, num); in xiic_xfer()
1339 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); in xiic_xfer()
1340 mutex_lock(&i2c->lock); in xiic_xfer()
1342 i2c->tx_msg = NULL; in xiic_xfer()
1343 i2c->rx_msg = NULL; in xiic_xfer()
1344 i2c->nmsgs = 0; in xiic_xfer()
1347 err = (i2c->state == STATE_DONE) ? num : -EIO; in xiic_xfer()
1349 mutex_unlock(&i2c->lock); in xiic_xfer()
1352 pm_runtime_mark_last_busy(i2c->dev); in xiic_xfer()
1353 pm_runtime_put_autosuspend(i2c->dev); in xiic_xfer()
1359 struct xiic_i2c *i2c = i2c_get_adapdata(adap); in xiic_xfer_atomic() local
1363 err = xiic_i2c_runtime_resume(i2c->dev); in xiic_xfer_atomic()
1367 i2c->atomic = true; in xiic_xfer_atomic()
1368 err = xiic_start_xfer(i2c, msgs, num); in xiic_xfer_atomic()
1372 err = readl_poll_timeout_atomic(i2c->base + XIIC_SR_REG_OFFSET, in xiic_xfer_atomic()
1379 spin_lock(&i2c->atomic_lock); in xiic_xfer_atomic()
1380 if (err || i2c->state) { in xiic_xfer_atomic()
1381 i2c->tx_msg = NULL; in xiic_xfer_atomic()
1382 i2c->rx_msg = NULL; in xiic_xfer_atomic()
1383 i2c->nmsgs = 0; in xiic_xfer_atomic()
1386 err = (i2c->atomic_xfer_state == STATE_DONE) ? num : -EIO; in xiic_xfer_atomic()
1387 spin_unlock(&i2c->atomic_lock); in xiic_xfer_atomic()
1389 i2c->atomic = false; in xiic_xfer_atomic()
1390 xiic_i2c_runtime_suspend(i2c->dev); in xiic_xfer_atomic()
1427 struct xiic_i2c *i2c; in xiic_i2c_probe() local
1435 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in xiic_i2c_probe()
1436 if (!i2c) in xiic_i2c_probe()
1443 i2c->quirks = data->quirks; in xiic_i2c_probe()
1446 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in xiic_i2c_probe()
1447 if (IS_ERR(i2c->base)) in xiic_i2c_probe()
1448 return PTR_ERR(i2c->base); in xiic_i2c_probe()
1457 platform_set_drvdata(pdev, i2c); in xiic_i2c_probe()
1458 i2c->adap = xiic_adapter; in xiic_i2c_probe()
1459 i2c_set_adapdata(&i2c->adap, i2c); in xiic_i2c_probe()
1460 i2c->adap.dev.parent = &pdev->dev; in xiic_i2c_probe()
1461 i2c->adap.dev.of_node = pdev->dev.of_node; in xiic_i2c_probe()
1462 snprintf(i2c->adap.name, sizeof(i2c->adap.name), in xiic_i2c_probe()
1465 mutex_init(&i2c->lock); in xiic_i2c_probe()
1466 spin_lock_init(&i2c->atomic_lock); in xiic_i2c_probe()
1468 i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL); in xiic_i2c_probe()
1469 if (IS_ERR(i2c->clk)) in xiic_i2c_probe()
1470 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), in xiic_i2c_probe()
1473 i2c->dev = &pdev->dev; in xiic_i2c_probe()
1474 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); in xiic_i2c_probe()
1475 pm_runtime_use_autosuspend(i2c->dev); in xiic_i2c_probe()
1476 pm_runtime_set_active(i2c->dev); in xiic_i2c_probe()
1477 pm_runtime_enable(i2c->dev); in xiic_i2c_probe()
1480 i2c->input_clk = clk_get_rate(i2c->clk); in xiic_i2c_probe()
1482 &i2c->i2c_clk); in xiic_i2c_probe()
1484 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ) in xiic_i2c_probe()
1485 i2c->i2c_clk = 0; in xiic_i2c_probe()
1489 pdev->name, i2c); in xiic_i2c_probe()
1496 i2c->singlemaster = in xiic_i2c_probe()
1504 i2c->endianness = LITTLE; in xiic_i2c_probe()
1505 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_i2c_probe()
1507 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); in xiic_i2c_probe()
1509 i2c->endianness = BIG; in xiic_i2c_probe()
1511 ret = xiic_reinit(i2c); in xiic_i2c_probe()
1517 /* add i2c adapter to i2c tree */ in xiic_i2c_probe()
1518 ret = i2c_add_adapter(&i2c->adap); in xiic_i2c_probe()
1520 xiic_deinit(i2c); in xiic_i2c_probe()
1527 i2c_new_client_device(&i2c->adap, pdata->devices + i); in xiic_i2c_probe()
1531 (unsigned long)res->start, irq, i2c->i2c_clk); in xiic_i2c_probe()
1544 struct xiic_i2c *i2c = platform_get_drvdata(pdev); in xiic_i2c_remove() local
1548 i2c_del_adapter(&i2c->adap); in xiic_i2c_remove()
1550 ret = pm_runtime_get_sync(i2c->dev); in xiic_i2c_remove()
1556 xiic_deinit(i2c); in xiic_i2c_remove()
1558 pm_runtime_put_sync(i2c->dev); in xiic_i2c_remove()
1583 MODULE_DESCRIPTION("Xilinx I2C bus driver");