Lines Matching +full:stm32mp1 +full:- +full:exti
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) STMicroelectronics 2017-2024
22 #include <dt-bindings/interrupt-controller/arm-gic.h>
131 __diag_ignore_all("-Woverride-init",
136 [0 ... (STM32MP_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
185 [0 ... (STM32MP_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
244 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); in stm32mp_exti_convert_type()
260 return -EINVAL; in stm32mp_exti_convert_type()
268 const struct stm32mp_exti_bank *bank = chip_data->reg_bank; in stm32mp_chip_suspend()
269 void __iomem *base = chip_data->host_data->base; in stm32mp_chip_suspend()
272 chip_data->rtsr_cache = readl_relaxed(base + bank->rtsr_ofst); in stm32mp_chip_suspend()
273 chip_data->ftsr_cache = readl_relaxed(base + bank->ftsr_ofst); in stm32mp_chip_suspend()
275 writel_relaxed(wake_active, base + bank->imr_ofst); in stm32mp_chip_suspend()
280 const struct stm32mp_exti_bank *bank = chip_data->reg_bank; in stm32mp_chip_resume()
281 void __iomem *base = chip_data->host_data->base; in stm32mp_chip_resume()
284 writel_relaxed(chip_data->rtsr_cache, base + bank->rtsr_ofst); in stm32mp_chip_resume()
285 writel_relaxed(chip_data->ftsr_cache, base + bank->ftsr_ofst); in stm32mp_chip_resume()
287 writel_relaxed(mask_cache, base + bank->imr_ofst); in stm32mp_chip_resume()
294 void __iomem *base = chip_data->host_data->base; in stm32mp_exti_write_bit()
295 u32 val = BIT(d->hwirq % IRQS_PER_BANK); in stm32mp_exti_write_bit()
303 void __iomem *base = chip_data->host_data->base; in stm32mp_exti_set_bit()
307 val |= BIT(d->hwirq % IRQS_PER_BANK); in stm32mp_exti_set_bit()
316 void __iomem *base = chip_data->host_data->base; in stm32mp_exti_clr_bit()
320 val &= ~BIT(d->hwirq % IRQS_PER_BANK); in stm32mp_exti_clr_bit()
329 const struct stm32mp_exti_bank *bank = chip_data->reg_bank; in stm32mp_exti_eoi()
331 raw_spin_lock(&chip_data->rlock); in stm32mp_exti_eoi()
333 stm32mp_exti_write_bit(d, bank->rpr_ofst); in stm32mp_exti_eoi()
334 stm32mp_exti_write_bit(d, bank->fpr_ofst); in stm32mp_exti_eoi()
336 raw_spin_unlock(&chip_data->rlock); in stm32mp_exti_eoi()
338 if (d->parent_data->chip) in stm32mp_exti_eoi()
345 const struct stm32mp_exti_bank *bank = chip_data->reg_bank; in stm32mp_exti_mask()
347 raw_spin_lock(&chip_data->rlock); in stm32mp_exti_mask()
348 chip_data->mask_cache = stm32mp_exti_clr_bit(d, bank->imr_ofst); in stm32mp_exti_mask()
349 raw_spin_unlock(&chip_data->rlock); in stm32mp_exti_mask()
351 if (d->parent_data->chip) in stm32mp_exti_mask()
358 const struct stm32mp_exti_bank *bank = chip_data->reg_bank; in stm32mp_exti_unmask()
360 raw_spin_lock(&chip_data->rlock); in stm32mp_exti_unmask()
361 chip_data->mask_cache = stm32mp_exti_set_bit(d, bank->imr_ofst); in stm32mp_exti_unmask()
362 raw_spin_unlock(&chip_data->rlock); in stm32mp_exti_unmask()
364 if (d->parent_data->chip) in stm32mp_exti_unmask()
371 const struct stm32mp_exti_bank *bank = chip_data->reg_bank; in stm32mp_exti_set_type()
372 struct hwspinlock *hwlock = chip_data->host_data->hwlock; in stm32mp_exti_set_type()
373 void __iomem *base = chip_data->host_data->base; in stm32mp_exti_set_type()
377 raw_spin_lock(&chip_data->rlock); in stm32mp_exti_set_type()
387 rtsr = readl_relaxed(base + bank->rtsr_ofst); in stm32mp_exti_set_type()
388 ftsr = readl_relaxed(base + bank->ftsr_ofst); in stm32mp_exti_set_type()
392 writel_relaxed(rtsr, base + bank->rtsr_ofst); in stm32mp_exti_set_type()
393 writel_relaxed(ftsr, base + bank->ftsr_ofst); in stm32mp_exti_set_type()
399 raw_spin_unlock(&chip_data->rlock); in stm32mp_exti_set_type()
406 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); in stm32mp_exti_set_wake()
408 raw_spin_lock(&chip_data->rlock); in stm32mp_exti_set_wake()
411 chip_data->wake_active |= mask; in stm32mp_exti_set_wake()
413 chip_data->wake_active &= ~mask; in stm32mp_exti_set_wake()
415 raw_spin_unlock(&chip_data->rlock); in stm32mp_exti_set_wake()
422 if (d->parent_data->chip) in stm32mp_exti_set_affinity()
434 for (i = 0; i < host_data->drv_data->bank_nr; i++) { in stm32mp_exti_suspend()
435 chip_data = &host_data->chips_data[i]; in stm32mp_exti_suspend()
436 stm32mp_chip_suspend(chip_data, chip_data->wake_active); in stm32mp_exti_suspend()
448 for (i = 0; i < host_data->drv_data->bank_nr; i++) { in stm32mp_exti_resume()
449 chip_data = &host_data->chips_data[i]; in stm32mp_exti_resume()
450 stm32mp_chip_resume(chip_data, chip_data->mask_cache); in stm32mp_exti_resume()
459 const struct stm32mp_exti_bank *bank = chip_data->reg_bank; in stm32mp_exti_retrigger()
460 void __iomem *base = chip_data->host_data->base; in stm32mp_exti_retrigger()
461 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); in stm32mp_exti_retrigger()
463 writel_relaxed(mask, base + bank->swier_ofst); in stm32mp_exti_retrigger()
469 .name = "stm32mp-exti",
481 .name = "stm32mp-exti-direct",
497 struct stm32mp_exti_host_data *host_data = dm->host_data; in stm32mp_exti_domain_alloc()
507 hwirq = fwspec->param[0]; in stm32mp_exti_domain_alloc()
508 if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK) in stm32mp_exti_domain_alloc()
509 return -EINVAL; in stm32mp_exti_domain_alloc()
512 chip_data = &host_data->chips_data[bank]; in stm32mp_exti_domain_alloc()
515 if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) { in stm32mp_exti_domain_alloc()
516 dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq); in stm32mp_exti_domain_alloc()
517 return -EPERM; in stm32mp_exti_domain_alloc()
520 event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst); in stm32mp_exti_domain_alloc()
526 if (host_data->dt_has_irqs_desc) { in stm32mp_exti_domain_alloc()
530 ret = of_irq_parse_one(host_data->dev->of_node, hwirq, &out_irq); in stm32mp_exti_domain_alloc()
534 if (of_node_to_fwnode(out_irq.np) != dm->parent->fwnode) in stm32mp_exti_domain_alloc()
535 return -EINVAL; in stm32mp_exti_domain_alloc()
543 if (!host_data->drv_data->desc_irqs) in stm32mp_exti_domain_alloc()
544 return -EINVAL; in stm32mp_exti_domain_alloc()
546 desc_irq = host_data->drv_data->desc_irqs[hwirq]; in stm32mp_exti_domain_alloc()
548 p_fwspec.fwnode = dm->parent->fwnode; in stm32mp_exti_domain_alloc()
565 void __iomem *base = h_data->base; in stm32mp_exti_chip_init()
567 bank = h_data->drv_data->exti_banks[bank_idx]; in stm32mp_exti_chip_init()
568 chip_data = &h_data->chips_data[bank_idx]; in stm32mp_exti_chip_init()
569 chip_data->host_data = h_data; in stm32mp_exti_chip_init()
570 chip_data->reg_bank = bank; in stm32mp_exti_chip_init()
572 raw_spin_lock_init(&chip_data->rlock); in stm32mp_exti_chip_init()
578 writel_relaxed(0, base + bank->imr_ofst); in stm32mp_exti_chip_init()
581 chip_data->event_reserved = readl_relaxed(base + bank->seccfgr_ofst); in stm32mp_exti_chip_init()
600 hwcfgr1 = readl_relaxed(host_data->base + EXTI_HWCFGR1); in stm32mp_exti_check_rif()
604 for (bank = 0; bank < host_data->drv_data->bank_nr; bank++) { in stm32mp_exti_check_rif()
607 cidcfgr = readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event)); in stm32mp_exti_check_rif()
610 host_data->chips_data[bank].event_reserved |= BIT(i); in stm32mp_exti_check_rif()
627 struct device *dev = &pdev->dev; in stm32mp_exti_probe()
628 struct device_node *np = dev->of_node; in stm32mp_exti_probe()
633 return -ENOMEM; in stm32mp_exti_probe()
636 host_data->dev = dev; in stm32mp_exti_probe()
640 if (ret == -EPROBE_DEFER) in stm32mp_exti_probe()
645 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); in stm32mp_exti_probe()
646 if (!host_data->hwlock) { in stm32mp_exti_probe()
648 return -EINVAL; in stm32mp_exti_probe()
650 } else if (ret != -ENOENT) { in stm32mp_exti_probe()
660 return -ENODEV; in stm32mp_exti_probe()
662 host_data->drv_data = drv_data; in stm32mp_exti_probe()
664 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, in stm32mp_exti_probe()
665 sizeof(*host_data->chips_data), in stm32mp_exti_probe()
667 if (!host_data->chips_data) in stm32mp_exti_probe()
668 return -ENOMEM; in stm32mp_exti_probe()
670 host_data->base = devm_platform_ioremap_resource(pdev, 0); in stm32mp_exti_probe()
671 if (IS_ERR(host_data->base)) in stm32mp_exti_probe()
672 return PTR_ERR(host_data->base); in stm32mp_exti_probe()
674 for (i = 0; i < drv_data->bank_nr; i++) in stm32mp_exti_probe()
681 dev_err(dev, "GIC interrupt-parent not found\n"); in stm32mp_exti_probe()
682 return -EINVAL; in stm32mp_exti_probe()
686 drv_data->bank_nr * IRQS_PER_BANK, in stm32mp_exti_probe()
691 dev_err(dev, "Could not register exti domain\n"); in stm32mp_exti_probe()
692 return -ENOMEM; in stm32mp_exti_probe()
699 host_data->dt_has_irqs_desc = of_property_present(np, "interrupts-extended"); in stm32mp_exti_probe()
705 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
706 { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data},
727 MODULE_DESCRIPTION("STM32MP EXTI driver");