37 #define MT9P031_CHIP_VERSION				0x00
38 #define		MT9P031_CHIP_VERSION_VALUE		0x1801
39 #define MT9P031_ROW_START				0x01
40 #define		MT9P031_ROW_START_MIN			0
43 #define MT9P031_COLUMN_START				0x02
44 #define		MT9P031_COLUMN_START_MIN		0
47 #define MT9P031_WINDOW_HEIGHT				0x03
51 #define MT9P031_WINDOW_WIDTH				0x04
55 #define MT9P031_HORIZONTAL_BLANK			0x05
56 #define		MT9P031_HORIZONTAL_BLANK_MIN		0
58 #define MT9P031_VERTICAL_BLANK				0x06
62 #define MT9P031_OUTPUT_CONTROL				0x07
65 #define		MT9P031_OUTPUT_CONTROL_DEF		0x1f82
66 #define MT9P031_SHUTTER_WIDTH_UPPER			0x08
67 #define MT9P031_SHUTTER_WIDTH_LOWER			0x09
71 #define	MT9P031_PLL_CONTROL				0x10
72 #define		MT9P031_PLL_CONTROL_PWROFF		0x0050
73 #define		MT9P031_PLL_CONTROL_PWRON		0x0051
74 #define		MT9P031_PLL_CONTROL_USEPLL		0x0052
75 #define	MT9P031_PLL_CONFIG_1				0x11
76 #define	MT9P031_PLL_CONFIG_2				0x12
77 #define MT9P031_PIXEL_CLOCK_CONTROL			0x0a
80 #define		MT9P031_PIXEL_CLOCK_DIVIDE(n)		((n) << 0)
81 #define MT9P031_RESTART					0x0b
83 #define		MT9P031_FRAME_RESTART			BIT(0)
84 #define MT9P031_SHUTTER_DELAY				0x0c
85 #define MT9P031_RST					0x0d
86 #define		MT9P031_RST_ENABLE			BIT(0)
87 #define MT9P031_READ_MODE_1				0x1e
88 #define MT9P031_READ_MODE_2				0x20
92 #define MT9P031_ROW_ADDRESS_MODE			0x22
93 #define MT9P031_COLUMN_ADDRESS_MODE			0x23
94 #define MT9P031_GLOBAL_GAIN				0x35
99 #define MT9P031_ROW_BLACK_TARGET			0x49
100 #define MT9P031_ROW_BLACK_DEF_OFFSET			0x4b
101 #define MT9P031_GREEN1_OFFSET				0x60
102 #define MT9P031_GREEN2_OFFSET				0x61
103 #define MT9P031_BLACK_LEVEL_CALIBRATION			0x62
104 #define		MT9P031_BLC_MANUAL_BLC			BIT(0)
105 #define MT9P031_RED_OFFSET				0x63
106 #define MT9P031_BLUE_OFFSET				0x64
107 #define MT9P031_TEST_PATTERN				0xa0
109 #define		MT9P031_TEST_PATTERN_ENABLE		BIT(0)
110 #define MT9P031_TEST_PATTERN_GREEN			0xa1
111 #define MT9P031_TEST_PATTERN_RED			0xa2
112 #define MT9P031_TEST_PATTERN_BLUE			0xa3
171 	if (ret < 0)  in mt9p031_set_output_control()
175 	return 0;  in mt9p031_set_output_control()
185 	if (ret < 0)  in mt9p031_set_mode2()
189 	return 0;  in mt9p031_set_mode2()
199 	if (ret < 0)  in mt9p031_reset()
201 	ret = mt9p031_write(client, MT9P031_RST, 0);  in mt9p031_reset()
202 	if (ret < 0)  in mt9p031_reset()
207 	if (ret < 0)  in mt9p031_reset()
211 					  0);  in mt9p031_reset()
241 	if (ret < 0)  in mt9p031_clk_setup()
258 		return 0;  in mt9p031_clk_setup()
274 		return 0;  in mt9p031_pll_enable()
278 	if (ret < 0)  in mt9p031_pll_enable()
283 	if (ret < 0)  in mt9p031_pll_enable()
287 	if (ret < 0)  in mt9p031_pll_enable()
302 		return 0;  in mt9p031_pll_disable()
322 	if (ret < 0)  in mt9p031_power_on()
337 		gpiod_set_value(mt9p031->reset, 0);  in mt9p031_power_on()
346 	return 0;  in mt9p031_power_on()
369 		return 0;  in __mt9p031_set_power()
373 	if (ret < 0)  in __mt9p031_set_power()
377 	if (ret < 0) {  in __mt9p031_set_power()
386 		if (ret < 0)  in __mt9p031_set_power()
417 	if (ret < 0)  in mt9p031_set_params()
420 	if (ret < 0)  in mt9p031_set_params()
423 	if (ret < 0)  in mt9p031_set_params()
426 	if (ret < 0)  in mt9p031_set_params()
439 	if (ret < 0)  in mt9p031_set_params()
443 	if (ret < 0)  in mt9p031_set_params()
453 	if (ret < 0)  in mt9p031_set_params()
456 	if (ret < 0)  in mt9p031_set_params()
473 		if (ret < 0)  in mt9p031_s_stream()
479 		if (ret < 0)  in mt9p031_s_stream()
484 						 MT9P031_OUTPUT_CONTROL_CEN, 0);  in mt9p031_s_stream()
485 		if (ret < 0)  in mt9p031_s_stream()
492 	if (ret < 0)  in mt9p031_s_stream()
496 	ret = mt9p031_set_output_control(mt9p031, 0,  in mt9p031_s_stream()
498 	if (ret < 0)  in mt9p031_s_stream()
508 	if (ret < 0)  in mt9p031_s_stream()
524 	return 0;  in mt9p031_enum_mbus_code()
542 	return 0;  in mt9p031_enum_frame_size()
583 	return 0;  in mt9p031_get_format()
621 	return 0;  in mt9p031_set_format()
636 		return 0;  in mt9p031_get_selection()
641 		return 0;  in mt9p031_get_selection()
696 	return 0;  in mt9p031_set_selection()
708 	crop = __mt9p031_get_pad_crop(mt9p031, sd_state, 0, which);  in mt9p031_init_state()
714 	format = __mt9p031_get_pad_format(mt9p031, sd_state, 0, which);  in mt9p031_init_state()
721 	return 0;  in mt9p031_init_state()
728 #define V4L2_CID_BLC_AUTO		(V4L2_CID_USER_BASE | 0x1002)
729 #define V4L2_CID_BLC_TARGET_LEVEL	(V4L2_CID_USER_BASE | 0x1003)
730 #define V4L2_CID_BLC_ANALOG_OFFSET	(V4L2_CID_USER_BASE | 0x1004)
731 #define V4L2_CID_BLC_DIGITAL_OFFSET	(V4L2_CID_USER_BASE | 0x1005)
738 	if (mt9p031->blc_auto->cur.val != 0) {  in mt9p031_restore_blc()
739 		ret = mt9p031_set_mode2(mt9p031, 0,  in mt9p031_restore_blc()
741 		if (ret < 0)  in mt9p031_restore_blc()
745 	if (mt9p031->blc_offset->cur.val != 0) {  in mt9p031_restore_blc()
748 		if (ret < 0)  in mt9p031_restore_blc()
752 	return 0;  in mt9p031_restore_blc()
764 		return 0;  in mt9p031_s_ctrl()
769 				    (ctrl->val >> 16) & 0xffff);  in mt9p031_s_ctrl()
770 		if (ret < 0)  in mt9p031_s_ctrl()
774 				     ctrl->val & 0xffff);  in mt9p031_s_ctrl()
806 					0, MT9P031_READ_MODE_2_COL_MIR);  in mt9p031_s_ctrl()
809 					MT9P031_READ_MODE_2_COL_MIR, 0);  in mt9p031_s_ctrl()
814 					0, MT9P031_READ_MODE_2_ROW_MIR);  in mt9p031_s_ctrl()
817 					MT9P031_READ_MODE_2_ROW_MIR, 0);  in mt9p031_s_ctrl()
825 		v4l2_ctrl_activate(mt9p031->blc_auto, ctrl->val == 0);  in mt9p031_s_ctrl()
826 		v4l2_ctrl_activate(mt9p031->blc_offset, ctrl->val == 0);  in mt9p031_s_ctrl()
831 			if (ret < 0)  in mt9p031_s_ctrl()
834 			return mt9p031_write(client, MT9P031_TEST_PATTERN, 0);  in mt9p031_s_ctrl()
837 		ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0);  in mt9p031_s_ctrl()
838 		if (ret < 0)  in mt9p031_s_ctrl()
840 		ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50);  in mt9p031_s_ctrl()
841 		if (ret < 0)  in mt9p031_s_ctrl()
843 		ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0);  in mt9p031_s_ctrl()
844 		if (ret < 0)  in mt9p031_s_ctrl()
849 					0);  in mt9p031_s_ctrl()
850 		if (ret < 0)  in mt9p031_s_ctrl()
853 		ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0);  in mt9p031_s_ctrl()
854 		if (ret < 0)  in mt9p031_s_ctrl()
863 				ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC,  in mt9p031_s_ctrl()
864 				ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0);  in mt9p031_s_ctrl()
865 		if (ret < 0)  in mt9p031_s_ctrl()
869 				     ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC);  in mt9p031_s_ctrl()
879 		if (ret < 0)  in mt9p031_s_ctrl()
882 		if (ret < 0)  in mt9p031_s_ctrl()
885 		if (ret < 0)  in mt9p031_s_ctrl()
894 	return 0;  in mt9p031_s_ctrl()
920 		.min		= 0,
924 		.flags		= 0,
930 		.min		= 0,
934 		.flags		= 0,
944 		.flags		= 0,
954 		.flags		= 0,
965 	int ret = 0;  in mt9p031_set_power()
969 	/* If the power count is modified from 0 to != 0 or from != 0 to 0,  in mt9p031_set_power()
974 		if (ret < 0)  in mt9p031_set_power()
980 	WARN_ON(mt9p031->power_count < 0);  in mt9p031_set_power()
999 	if (ret < 0) {  in mt9p031_registered()
1010 			"0x%04x\n", data);  in mt9p031_registered()
1014 	dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n",  in mt9p031_registered()
1017 	return 0;  in mt9p031_registered()
1027 	return mt9p031_set_power(subdev, 0);  in mt9p031_close()
1089 	return 0;  in mt9p031_parse_properties()
1117 	mt9p031->regulators[0].supply = "vdd";  in mt9p031_probe()
1122 	if (ret < 0) {  in mt9p031_probe()
1139 			  V4L2_CID_HFLIP, 0, 1, 1, 0);  in mt9p031_probe()
1141 			  V4L2_CID_VFLIP, 0, 1, 1, 0);  in mt9p031_probe()
1147 			  ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0,  in mt9p031_probe()
1148 			  0, mt9p031_test_pattern_menu);  in mt9p031_probe()
1150 	for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i)  in mt9p031_probe()
1172 	if (ret < 0)  in mt9p031_probe()
1191 	if (ret < 0) {  in mt9p031_probe()